Semiconductor device and manufacturing method

Patent metadata

Field	Value
Publication number	US-12527016-B2
Application number	US-202318304378-A
Country	US
Kind code	B2
Filing date	Apr 21, 2023
Priority date	May 19, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

Provided is a semiconductor device including: a first trench contact portion provided to an inside of a contact region; a second trench contact portion provided to an inside of an emitter region; a first plug portion of a second conductivity type, which is provided in contact with a lower end of the first trench contact portion and has a higher concentration than a base region; and a second plug portion of a second conductivity type, which is provided in contact with a lower end of the second trench contact portion, is provided to a position closer to a lower surface than the first plug portion, and has a higher concentration than the base region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor substrate including an upper surface, a lower surface, and a drift region of a first conductivity type; a base region of a second conductivity type, which is provided between the upper surface and the drift region; a gate trench portion which is provided from the upper surface to the drift region and is provided so as to extend in a longitudinal direction in the upper surface; an emitter region of a first conductivity type, which is provided between the upper surface and the base region and is in contact with the gate trench portion; a contact region of a second conductivity type, which is provided between the upper surface and the base region and is arranged alternately with the emitter region in a longitudinal direction of the gate trench portion; a first trench contact portion provided from the upper surface to an inside of the contact region; a second trench contact portion provided from the upper surface to an inside of the emitter region; a first plug portion of a second conductivity type, which is provided in contact with a lower end of the first trench contact portion and has a higher concentration than the base region; and a second plug portion of a second conductivity type, which is provided in contact with a lower end of the second trench contact portion, is provided to a position closer to the lower surface than the first plug portion, and has a higher concentration than the base region.

2 . The semiconductor device according to claim 1 , wherein
the contact region, the first plug portion, and the second plug portion contain acceptors of a same element.

3 . The semiconductor device according to claim 1 , wherein
a lower end of the second plug portion is arranged closer to the lower surface than a lower end of the emitter region.

4 . The semiconductor device according to claim 3 , wherein
the lower end of the second plug portion is arranged closer to the upper surface than a lower end of the contact region.

5 . The semiconductor device according to claim 1 , wherein
a lower end of the first plug portion is arranged at a same depth position as a lower end of the contact region or is arranged closer to the upper surface than the lower end of the contact region.

6 . The semiconductor device according to claim 1 , wherein
a depth position of a lower end of the second plug portion is arranged 0.1 μm or more closer to the lower surface than a depth position of a lower end of the first plug portion.

7 . The semiconductor device according to claim 6 , wherein
the depth position of the lower end of the second plug portion is arranged 0.3 μm or more closer to the lower surface than the depth position of the lower end of the first plug portion.

8 . The semiconductor device according to claim 1 , wherein
a peak value of an acceptor concentration of the second plug portion is smaller than a peak value of an acceptor concentration of the first plug portion.

9 . The semiconductor device according to claim 1 , further comprising:
a trench portion which is provided adjacent to the gate trench portion in an array direction perpendicular to the longitudinal direction, is provided from the upper surface to the drift region, and is provided so as to extend in the longitudinal direction; and a mesa portion sandwiched between the gate trench portion and the trench portion, wherein a width of the mesa portion in the array direction is smaller than a width of the gate trench portion.

10 . The semiconductor device according to claim 1 , wherein
the first plug portion includes a first portion in contact with a side surface of the first trench contact portion, the second plug portion includes a second portion in contact with a side surface of the second trench contact portion, and a width of the second portion is smaller than a width of the first portion.

11 . The semiconductor device according to claim 1 , wherein
the first plug portion and the second plug portion contain boron, the semiconductor substrate contains silicon, a silicide portion is provided at a boundary between: the first trench contact portion and the second trench contact portion; and the semiconductor substrate, and the silicide portion contains boron.

12 . A semiconductor device, comprising:
a semiconductor substrate including an upper surface, a lower surface, and a drift region of a first conductivity type; a base region of a second conductivity type, which is provided between the upper surface and the drift region; a gate trench portion which is provided from the upper surface to the drift region and is provided so as to extend in a longitudinal direction in the upper surface; an emitter region of a first conductivity type, which is provided between the upper surface and the base region and is in contact with the gate trench portion; a contact region of a second conductivity type, which is provided between the upper surface and the base region and is arranged alternately with the emitter region in a longitudinal direction of the gate trench portion; a trench contact portion which is provided from the upper surface to an inside of the contact region and also from the upper surface to an inside of the emitter region; and a plug portion of a second conductivity type, which is, in both the emitter region and the contact region, provided in contact with a lower end of the trench contact portion, has a higher concentration than the base region, and is provided to be shallower than the contact region.

13 . The semiconductor device according to claim 12 , wherein
the trench contact portion includes:
a first trench contact portion provided from the upper surface to the inside of the contact region; and
a second trench contact portion provided from the upper surface to the inside of the emitter region, and
the plug portion includes:
a first plug portion provided in contact with a lower end of the first trench contact portion; and
a second plug portion which is provided in contact with a lower end of the second trench contact portion and is provided to a same depth as the first plug portion.

14 . The semiconductor device according to claim 13 , wherein
both the first plug portion and the second plug portion are provided to be shallower than the contact region.

15 . The semiconductor device according to claim 14 , wherein
a distance from the upper surface of the semiconductor substrate to a lower end of the contact region is 1.5 times or more of a distance from the upper surface of the semiconductor substrate to lower ends of the first plug portion and the second plug portion.

16 . The semiconductor device according to claim 12 , wherein
the trench contact portion includes:
a first trench contact portion provided from the upper surface to the inside of the contact region; and
a second trench contact portion provided from the upper surface to the inside of the emitter region, and
the plug portion includes:
a first plug portion provided in contact with a lower end of the first trench contact portion; and
a second plug portion which is provided in contact with a lower end of the second trench contact portion and is provided to a position closer to the lower surface than the first plug portion.

17 . A manufacturing method, comprising:
forming an upper surface side structure by forming, in a semiconductor substrate including an upper surface, a lower surface, and a drift region of a first conductivity type, a base region of a second conductivity t

Assignees

• Fuji Electric Co Ltd

Inventors

• Noguchi Seiji
• Hamasaki Ryutaro
• Ozaki Daisuke
• Sakurai Yosuke
• Yamada Takuya

Classifications

• H10D64/231

  Emitter or collector electrodes for bipolar transistors · CPC title

• H10D62/137

  Collector regions of BJTs · CPC title

• H10D62/133

  Emitter regions of BJTs · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title

• H10D30/0295

  using recessing of the source electrodes · CPC title