System for and method of analog to digital conversion using calibration

Patent metadata

Field	Value
Publication number	US-12525987-B2
Application number	US-202318361649-A
Country	US
Kind code	B2
Filing date	Jul 28, 2023
Priority date	Jul 28, 2023
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

The systems and methods discussed herein related to analog to digital conversion. An apparatus can include an analog to digital converter including a loop circuit and a comparator circuit. The apparatus can also include a first circuit configured to provide comparator offset calibration for the comparator circuit and a second circuit configured to provide loop calibration for the loop circuit.

First claim

What is claimed is:

1 . An apparatus, comprising:
an analog to digital converter comprising a loop circuit and a comparator circuit; a first circuit configured to provide comparator offset calibration for the comparator circuit; and a second circuit configured to provide loop calibration for the loop circuit, the second circuit comprising:
a frequency estimator; and
an analyzer configured to:
receive a first frequency measurement from the frequency estimator for a first stage of the loop calibration;
adjust a resistance or a capacitance of the first stage of the loop calibration;
receive a second frequency measurement from the frequency estimator for a second stage of the loop calibration; and
adjust a resistance or a capacitance of the second stage of the loop calibration.

2 . The apparatus of claim 1 , wherein the apparatus is part of a transceiver provided in a single integrated circuit (IC) package.

3 . The apparatus of claim 1 , wherein the first circuit is configured to detect toggling of a comparator output.

4 . The apparatus of claim 1 , wherein the comparator circuit comprises seven one bit comparators.

5 . The apparatus of claim 1 , wherein the second circuit is configured to:
adjust a capacitance of the loop circuit; or adjust a stage of the loop calibration.

6 . An analog to digital converter, comprising:
a loop circuit having a first stage and a second stage; and a first circuit configured to provide loop calibration for the first stage and loop calibration for the second stage, and the first circuit comprising:
a frequency estimator; and
an analyzer configured to:
receive a first frequency measurement from the frequency estimator for the first stage;
adjust a resistance or a capacitance in the first stage;
receive a second frequency measurement from the frequency estimator for the second stage; and
adjust a resistance or a capacitance in the second stage.

7 . The analog to digital converter of claim 6 , further comprising an integrated circuit (IC) package containing the first circuit and the loop circuit.

8 . The analog to digital converter of claim 6 , further comprising:
a comparator circuit coupled to the second stage.

9 . The analog to digital converter of claim 8 , further comprising:
a second circuit configured to provide comparator offset calibration for the comparator circuit.

10 . The analog to digital converter of claim 9 , wherein the second circuit is configured to detect toggling of a comparator output.

11 . The analog to digital converter of claim 6 , wherein the first circuit adjusts a capacitance of the first stage.

12 . The analog to digital converter of claim 6 , further comprising a comparator circuit.

13 . The analog to digital converter of claim 12 , further comprising a second circuit configured to provide comparator offset calibration for the comparator circuit.

14 . The analog to digital converter of claim 13 , wherein the second circuit is configured to detect toggling of a comparator output.

15 . The analog to digital converter of claim 12 , wherein the comparator circuit comprises seven one bit comparators.

16 . The analog to digital converter of claim 6 , wherein the analog to digital converter is part of a transceiver provided in a single IC package.

17 . A method comprising:
providing comparator offset calibration for a comparator circuit of an analog to digital converter using on-chip circuitry; and providing loop calibration for a loop circuit of the analog to digital converter using the on-chip circuitry, and the on-chip circuitry comprising:
a frequency estimator; and
an analyzer configured to:
receive a first frequency measurement from the frequency estimator for a first stage of the loop calibration;
adjust a resistance or a capacitance in the first stage;
receive a second frequency measurement from the frequency estimator for a second stage of the loop calibration; and
adjust a resistance or a capacitance in the second stage.

18 . The method of claim 17 , wherein the comparator circuit and the loop circuit are in an in-phase path.

19 . The method of claim 17 , wherein the comparator circuit and the loop circuit are in a quadrature path.

20 . The method of claim 17 , wherein the comparator offset calibration comprises detecting toggling of a comparator output.

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Zhou Jun
• Chi Hongwu

Classifications

• H03M3/386

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M3/384 Primary

  Offset correction (removal of offset already present on the analogue input signal H03M3/494) · CPC title

• H03M1/40

  recirculation type · CPC title

• H03M1/1014 Primary

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M3/402

  Arrangements specific to bandpass modulators · CPC title