Dynamic voltage reference for delta-sigma analog-to-digital converter (ADC) with temperature trim calibration

Patent metadata

Field	Value
Publication number	US-10958285-B2
Application number	US-202016881642-A
Country	US
Kind code	B2
Filing date	May 22, 2020
Priority date	May 24, 2019
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

A calibratable switched-capacitor voltage reference and an associated calibration method are described. The voltage reference includes dynamic diode elements providing diode voltages, input capacitor(s) for sampling input voltages, base-emitter capacitor(s) for sampling one diode voltage with respect to a ground, dynamically trimmable capacitor(s) for sampling the one diode voltage with respect to another diode voltage, and an operational amplifier coupled to the capacitors for providing reference voltage(s) based on the sampled input and diode voltages and on trims of the trimmable capacitor(s). The voltage reference can be configured as a first integrator of a modulator stage of a delta-sigma analog-to-digital converter.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a single-ended or differential switched-capacitor voltage reference comprising:
dynamic diode elements configured to provide first and second diode voltages;
an input capacitor configured to sample an input voltage;
a base-emitter capacitor configured to sample the first diode voltage with respect to a ground;
a dynamically trimmable capacitor configured to sample the first diode voltage with respect to the second diode voltage; and
an operational amplifier (op amp) coupled at an op amp input to the input capacitor, the base-emitter capacitor, and the dynamically trimmable capacitor, the op amp configured to provide a reference voltage based on the sampled input voltage, the first and second diode voltages, and a trim of the trimmable capacitor.

2. The IC of claim 1 , wherein the voltage reference is configured as a first integrator of a modulator stage of a delta-sigma analog-to-digital converter (ADC).

3. The IC of claim 2 , wherein the ADC is configured to output a digital code indicative of capacitor mismatch.

4. The IC of claim 3 , wherein the trimmable capacitor is trimmed based on the digital code.

5. The IC of claim 1 , wherein the voltage reference comprises an external voltage switch coupled to an input of the base-emitter capacitor and configured to selectably uncouple the base-emitter capacitor from the dynamic diode elements and to couple the base-emitter capacitor to an externally supplied test voltage, such that the base-emitter capacitor samples the externally supplied test voltage instead of the first diode voltage.

6. The IC of claim 5 , wherein the externally supplied test voltage is configured to be provided as a minimum temperature coefficient voltage at which the voltage reference has a minimum temperature coefficient.

7. The IC of claim 6 , wherein the dynamic diode elements comprise stacks of M series diodes configured to adjust the first diode voltage to a minimum temperature coefficient voltage that is an M-multiple of a bandgap voltage.

8. The IC of claim 7 , wherein the bandgap voltage is the bandgap voltage of silicon.

9. The IC of claim 1 , wherein the voltage reference comprises a trimmable capacitor grounding switch coupled to an input of the trimmable capacitor and configured to selectably uncouple the trimmable capacitor from the dynamic diode elements and couple the trimmable capacitor to the ground.

10. A method comprising:
grounding an input to a trimmable capacitor of a differential switched-capacitor voltage reference, the voltage reference configured as a first integrator of a delta-sigma analog-to-digital converter (ADC);
applying an external test reference voltage to a base-emitter capacitor of the voltage reference;
applying a maximum external input voltage to an input capacitor of the voltage reference;
recording and storing an uncorrected output code from the ADC;
applying dynamic diode element voltages to the base-emitter capacitor and the trimmable capacitor;
applying the maximum external input voltage to the input capacitor; and
adjusting trim control bits controlling a trim of the trimmable capacitor until a new output code from the ADC matches the stored uncorrected output code.

11. The method of claim 10 , further comprising applying digital gain calibration to adjust the new output code to a target code with the maximum external input voltage applied.

12. The method of claim 10 , wherein the external test reference voltage is an expected minimum temperature coefficient voltage (“target voltage”) of the voltage reference.

13. The method of claim 12 , wherein the dynamic diode element voltages are supplied using a dynamic element-matching diode array comprising M diodes in series and the dynamic element-matching diode array is configured to adjust at least one of the dynamic diode element voltages to the target voltage that is an M-multiple of a bandgap voltage.

14. The method of claim 13 , wherein the bandgap voltage is the bandgap voltage of silicon.

15. The method of claim 10 , wherein the method is performed at a single temperature point.

16. The method of claim 10 , wherein the method is performed during a post-fabrication test/calibration phase, during which a fabricated integrated circuit (IC) that includes the voltage reference is connected to test/calibration equipment.

17. A system comprising:
a delta-sigma analog-to-digital converter (ADC) comprising:
an analog modulator comprising a single-ended or differential switched-capacitor voltage reference configured as a first-stage integrator of the analog modulator, the voltage reference comprising a dynamically trimmable capacitor configured to receive a trim control signal to adjust its capacitance;
a multi-bit output configured to produce a digital output code based on an input voltage provided to the voltage reference and the trim control signals.

18. The system of claim 17 , further comprising a digital-logic gain calibration circuit coupled to the multi-bit output of the ADC and configured to adjust the digital output code with a gain trim to provide a gain-calibrated output code.

19. The system of claim 18 , wherein the gain calibration circuit is configured to calibrate the system to a target code with a stable input voltage.

20. The system of claim 19 , wherein the target code is based on an external input voltage applied to base-emitter capacitors of the voltage reference, divided by a minimum temperature coefficient voltage of the voltage reference (“target voltage”), multiplied by a maximum output code of the ADC determined by the number of bits in the multi-bit output of the ADC.

Assignees

• Texas Instruments Inc

Inventors

• Hunter Bradford Lawrence
• Li Xiaopeng

Classifications

• H03M3/382

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error · CPC title

• H03M3/34

  by chopping · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/1061

  using digitally programmable trimming circuits · CPC title

• H03M3/384 Primary

  Offset correction (removal of offset already present on the analogue input signal H03M3/494) · CPC title