Sigma-delta analog-to-digital converter capable of reducing idle tones while alternately conducting signal conversion and comparator offset calibration

Patent metadata

Field	Value
Publication number	US-10998916-B2
Application number	US-202016742223-A
Country	US
Kind code	B2
Filing date	Jan 14, 2020
Priority date	Jan 18, 2019
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A sigma-delta analog-to-digital converter includes: a subtractor for subtracting a feedback signal from an analog input signal; a loop filter for processing the output signal from the subtractor to generate a filtered signal; a signal comparing circuit for selectively operating in an offset detection mode or a signal comparison mode, wherein the signal comparing circuit generates an error signal irrelevant to the relative magnitude between the filtered signal and a reference signal in the offset detection mode, and generates a comparison signal corresponding to the relative magnitude between the filtered signal and the reference signal in the signal comparison mode; an offset calibration control circuit for calibrating the offset of the signal comparing circuit and for controlling the signal comparing circuit to alternately switch between the offset detection mode and the signal comparison mode; and a digital-to-analog converter for generating the feedback signal according to the comparison signal.

First claim

What is claimed is:

1. A sigma-delta analog-to-digital converter ( 100 ), comprising:
a subtractor ( 110 ), arranged to operably subtract a feedback signal (Sfb) from an analog input signal (Sin);
a loop filter ( 120 ), coupled with the subtractor ( 110 ), and arranged to operably process an output signal of the subtractor ( 110 ) to generate a filtered signal (SF);
a first signal comparing circuit ( 130 ), coupled with the loop filter ( 120 ) and a first reference signal (VR 1 ), and arranged to selectively operate in an offset detection mode or a signal comparison mode, wherein the first signal comparing circuit ( 130 ) generates a first error signal (ERR 1 ) irrelevant to a relative magnitude between the filtered signal (SF) and the first reference signal (VR 1 ) when operating in the offset detection mode, while the first signal comparing circuit ( 130 ) generates a first comparison signal (CMP 1 ) corresponding to a relative magnitude between the filtered signal (SF) and the first reference signal (VR 1 ) when operating in the signal comparison mode;
an offset calibration control circuit ( 150 ), coupled with the first signal comparing circuit ( 130 ), and arranged to operably calibrate an offset of the first signal comparing circuit ( 130 ) according to the first error signal (ERR 1 ), and to operably control the first signal comparing circuit ( 130 ) to alternately switch between the offset detection mode and the signal comparison mode; and
a digital-to-analog converter ( 160 ), coupled with the subtractor ( 110 ) and an output terminal of the first signal comparing circuit ( 130 ), and arranged to operably generate the feedback signal (Sfb) according to the first comparison signal (CMP 1 );
wherein the first signal comparing circuit ( 130 ) comprises:
a first comparator ( 132 ), having a first input terminal ( 322 ), a second input terminal ( 324 ), a third input terminal ( 326 ), and a fourth input terminal ( 328 ), and arranged to operably compare signals of the first input terminal ( 322 ) and the second input terminal ( 324 ), and compare signals of the third input terminal ( 326 ) and the fourth input terminal ( 328 ), so as to generate a corresponding output signal, wherein the fourth input terminal ( 328 ) is coupled with a first common-mode signal (VCM 1 ), and
a first signal selection circuit ( 134 ), coupled with the loop filter ( 120 ), the first input terminal ( 322 ) of the first comparator ( 132 ), the second input terminal ( 324 ) of the first comparator ( 132 ), the offset calibration control circuit ( 150 ), the first reference signal (VR 1 ), and a first fixed-voltage signal (VF 1 ), wherein in the offset detection mode, the first signal selection circuit ( 134 ) couples both the first input terminal ( 322 ) and the second input terminal ( 324 ) with the first fixed-voltage signal (VF 1 ), so that the first comparator ( 132 ) generates the first error signal (ERR 1 ), while in the signal comparison mode, the first signal selection circuit ( 134 ) respectively couples the first input terminal ( 322 ) and the second input terminal ( 324 ) with the filtered signal (SF) and the first reference signal (VR 1 ), so that the first comparator ( 132 ) generates the first comparison signal (CMP 1 ).

2. The sigma-delta analog-to-digital converter ( 100 ) of claim 1 , wherein the first signal comparing circuit ( 130 ) further comprises:
a first compensation circuit ( 136 ), coupled with the offset calibration control circuit ( 150 ) and the third input terminal ( 326 ) of the first comparator ( 132 ), and arranged to operably compensate the signal of the third input terminal ( 326 ) of the first comparator ( 132 ) under control of the offset calibration control circuit ( 150 );
wherein in every predetermined number of clock periods of a clock (CLK), the offset calibration control circuit ( 150 ) is further arranged to operably control the first signal selection circuit ( 134 ) to switch to the offset detection mode at least one time, and to switch to the signal comparison mode at least one time; and the offset calibration control circuit ( 150 ) is further arranged to operably adjust a signal compensation amount with respect to the first compensation circuit ( 136 ) according to the first error signal (ERR 1 ).

3. The sigma-delta analog-to-digital converter ( 100 ) of claim 2 , wherein the first signal selection circuit ( 134 ) comprises:
a first switch circuit ( 342 ), coupled among the loop filter ( 120 ), the first fixed-voltage signal (VF 1 ), and the first input terminal ( 322 ), and controlled by the offset calibration control circuit ( 150 ); and
a second switch circuit ( 344 ), coupled among the first reference signal (VR 1 ), the first fixed-voltage signal (VF 1 ), and the second input terminal ( 324 ), and controlled by the offset calibration control circuit ( 150 );
wherein in the offset detection mode, the offset calibration control circuit ( 150 ) controls the first switch circuit ( 342 ) to couple the first input terminal ( 322 ) with the first fixed-voltage signal (VF 1 ), and controls the second switch circuit ( 344 ) to couple the second input terminal ( 324 ) with the first fixed-voltage signal (VF 1 ); while in the signal comparison mode, the offset calibration control circuit ( 150 ) controls the first switch circuit ( 342 ) to couple the first input terminal ( 322 ) with the filtered signal (SF), and controls the second switch circuit ( 344 ) to couple the second input terminal ( 324 ) with the first reference signal (VR 1 ).

4. The sigma-delta analog-to-digital converter ( 100 ) of claim 3 , wherein the first compensation circuit ( 136 ) comprises:
a compensation capacitor ( 362 ), wherein a first terminal of the compensation capacitor ( 362 ) is coupled with the third input terminal ( 326 ), while a second terminal of the compensation capacitor ( 362 ) is coupled with a fixed-voltage terminal; and
a first adjusting circuit ( 364 ), coupled with the first terminal of the compensation capacitor ( 362 ), and arranged to operably charge the compensation capacitor ( 362 ) under control of the offset calibration control circuit ( 150 ).

5. The sigma-delta analog-to-digital converter ( 100 ) of claim 4 , wherein the first compensation circuit ( 136 ) further comprises:
a second adjusting circuit ( 366 ), coupled with the first terminal of the compensation capacitor ( 362 ), and arranged to operably discharge the compensation capacitor ( 362 ) under control of the offset calibration control circuit ( 150 ).

6. The sigma-delta analog-to-digital converter ( 100 ) of claim 5 , wherein the first compensation circuit ( 136 ) further comprises:
a third switch circuit ( 368 ), arranged to selectively couple the third input terminal ( 326 ) of the first comparator ( 132 ) with the first common-mode signal (VCM 1 ) under control of the offset calibration control circuit ( 150 ).

7. The sigma-delta analog-to-digital converter ( 100 ) of claim 4 , wherein the first compensation circuit ( 136 ) further comprises:
a third switch circuit ( 368 ), arranged to selectively couple the third input terminal ( 326 ) of the first comparator ( 132 ) with the first common-mode signal (VCM 1 ) under control of the offset calibration control circuit ( 150 ).

8. The sigma-delta analog-to-digital converter ( 100 ) of claim 2 , further comprising:
a second signal comparing circuit ( 140 ), coupled with the loop filter ( 120 ), the offset calibration control circuit ( 150 ), the digital-to-analog converter ( 160 ), and a second reference signal (VRn), and arranged to selectively operate in the offset detection mode or the signal comparison mode, wherein when operating in the offset detection mode, the second signal comparing circuit ( 140 ) generate

Assignees

• Realtek Semiconductor Corp

Inventors

• Wang Chih-Chiang

Classifications

• H03M3/37

  Compensation or reduction of delay or phase error · CPC title

• H03M3/436

  characterised by the order of the loop filter, e.g. error feedback type · CPC title

• H03K5/24 Primary

  the characteristic being amplitude · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/328

  using dither · CPC title