Power amplifier and Doherty amplifier comprising the same

Patent metadata

Field	Value
Publication number	US-12525933-B2
Application number	US-202217935273-A
Country	US
Kind code	B2
Filing date	Sep 26, 2022
Priority date	Oct 4, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

Example embodiments relate to power amplifiers and Doherty amplifiers that include the same. One example embodiment includes a power amplifier. The power amplifier includes one or more radiofrequency (RF) output terminals. The power amplifier also includes a Gallium Nitride (GaN) semiconductor die on which a power field-effect transistor (FET) is integrated. The FET includes a plurality of FET cells that are adjacently arranged in a row. The FET cells are connected either directly or indirectly to the one or more RF output terminals via a respective first inductor. For FET cells arranged at opposing ends of the row of FET cells, a total FET cell gate width and an inductance of the first inductor is larger and smaller than the total FET cell gate width and inductance of the first inductor for one or more FET cells arranged in the middle of the row of FET cells, respectively.

First claim

What is claimed is:

1 . A power amplifier comprising:
one or more radiofrequency (RF) output terminals; and a Gallium Nitride (GaN) semiconductor die on which a power field-effect transistor (FET) is integrated, said FET comprising a plurality of FET cells that are adjacently arranged in a row, wherein each of the FET cells is connected to a respective first inductor, wherein each of the respective first inductors is connected either directly or indirectly to one of the one or more RF output terminals, wherein a total FET cell gate width of a FET cell arranged at an end of the row of FET cells is larger than the total FET cell gate width for a FET cell arranged in or near the middle of the row of FET cells, and wherein an inductance of the first inductor of the FET cell arranged at the end of the row of FET cells is smaller than the inductance of the first inductor of the FET cell arranged in or near the middle of the row of FET cells.

2 . The power amplifier according to claim 1 , wherein said plurality of FET cells is an even number of FET cells, wherein the row of FET cells extends from a first outer FET cell to a first center FET cell and from a second center FET cell to a second outer FET cell, wherein the first and second center FET cells are adjacently arranged, wherein the first outer FET cell and the second outer FET cell are arranged at opposite ends of the row of FET cells,
wherein the total FET cell gate width and the inductance of the first inductor decreases and increases, respectively, from the first outer FET cell to the first center FET cell and increases and decreases, respectively, from the second center FET cell to the second outer FET cell, and wherein said increase and decrease of the inductance of the first inductor and said increase and decrease of the total FET cell gate width are monotonic.

3 . The power amplifier according to claim 1 , wherein said plurality of FET cells is an odd number of FET cells, wherein the row of unit cells extends from a first outer FET cell to a center FET cell and from the center FET cell to a second outer FET cell, wherein the first and second outer FET cells are arranged at opposite ends of the row of FET cells,
wherein the total FET cell gate width and the inductance of the first inductor decreases and increases, respectively from the first outer FET cell to the center FET cell and increases and decreases, respectively, from the center FET cell to the second outer FET cell, and wherein said increase and decrease of the inductance of the first inductor and said increase and decrease of the total FET cell gate width are monotonic.

4 . The power amplifier according to claim 3 , wherein during predefined operating conditions, each FET cell sees an output impedance at its intrinsic drain, wherein said increase or decrease in total FET cell gate width and said corresponding decrease or increase in inductance of the first inductor are configured for minimizing a difference between the output impedances seen by the plurality of FET cells during said predefined operating conditions, and wherein the output impedance is a large-signal impedance or a small-signal impedance.

5 . The power amplifier according to claim 4 , wherein the predefined operating conditions are conditions at which the output power of the power amplifier is saturated at a frequency within an operational bandwidth of the power amplifier.

6 . The power amplifier according to claim 1 , wherein, for the purpose of decreasing or increasing the total FET cell gate width, the number of gate fingers or the gate width of the gate finger(s) differs among the FET cells.

7 . The power amplifier according to claim 1 , wherein the first inductor for each FET cell is formed using one or more first output bondwires among a plurality of first output bondwires, wherein, for the purpose of decreasing or increasing the inductance of the first inductor, and wherein the number of first output bondwires, the height of the first output bondwire(s), or the length of the first output bondwire(s) differs among the FET cells.

8 . The power amplifier according to claim 1 , wherein the FET cells comprise:
a gate base and one or more gate fingers extending from the gate base, wherein the total FET cell gate width corresponds to the combined width of the one or more gate fingers; a drain base and one or more drain fingers extending from the drain base; one or more drain bond pads integrally formed or connected to the drain base; and one or more source contacts, wherein for each pair of adjacently arranged FET cells, the corresponding gate bases are in physical and electrical contact and the corresponding drain bases are in physical and electrical contact.

9 . The power amplifier according to claim 8 , wherein the first inductor for each FET cell is formed using one or more first output bondwires among a plurality of first output bondwires, wherein, for the purpose of decreasing or increasing the inductance of the first inductor, the number of first output bondwires, the height of the first output bondwire(s), or the length of the first output bondwire(s) differs among the FET cells, and wherein the power amplifier further comprises:
a plurality of output capacitive elements, each having a first terminal and a grounded second terminal; and a plurality of second output bondwires, wherein, for each FET cell, the one or more drain bond pads are electrically connected to the first terminal of a respective output capacitive element among the plurality of output capacitive elements using one or more first output bondwires among the plurality of first output bondwires, said one or more first output bondwires at least partially forming, for said FET cell, the first inductor arranged between the drain base of that FET cell and the first terminal of the output capacitive element to which that FET cell is connected, wherein each of the first terminals of the output capacitive elements is connected to a respective second bondwire of the plurality of second output bondwires, and wherein each of the plurality of second output bondwires is connected either directly or indirectly to one of the one or more RF output terminals.

10 . The power amplifier according to claim 9 , wherein the first terminals of the output capacitive elements are physically connected for forming a single terminal, and wherein the output capacitive elements correspond to segments of a single capacitor, the power amplifier comprising an output substrate on which the output capacitive elements are integrated.

11 . The power amplifier according to claim 9 , wherein said one or more output capacitive elements, said plurality of first output bondwires, and said plurality of second output bondwires jointly form output impedance matching stages between the drain bases of the FET cells and the one or more RF output terminals.

12 . The power amplifier according to claim 1 , further comprising one or more RF input terminals,
wherein each of the FET cells is connected to a respective second inductor, wherein each of the respective second inductors is connected either directly or indirectly to one of the one or more RF input terminals, and wherein an inductance of the second inductor of the FET cell arranged at the end of the row of FET cells is smaller than the inductance of the second inductor of the FET cell arranged in or near the middle of the row of FET cells.

13 . The power amplifier according to claim 12 , wherein the second inductor for each FET cell is formed using one or more first input bondwires among a plurality of first input bondwires, and wherein, for the purpose o

Assignees

• Ampleon Netherlands Bv

Inventors

• Geng Zhi
• Zhu Yi

Classifications

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/206

  Wires · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title