Packaged electronic circuits having moisture protection encapsulation and methods of forming same

Patent metadata

Field	Value
Publication number	US-10811370-B2
Application number	US-201815960693-A
Country	US
Kind code	B2
Filing date	Apr 24, 2018
Priority date	Apr 24, 2018
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

First claim

What is claimed is:

1. A method of fabricating an electronic circuit, the method comprising:
forming a first polymer layer at a first temperature on a portion of a first metal layer;
forming a second metal layer on the first polymer layer opposite the first metal layer;
forming a dielectric layer at a second temperature on the second metal layer and on the first polymer layer; and
forming a second polymer layer at a third temperature on the dielectric layer,
wherein the dielectric layer comprises a second dielectric layer, the method further comprising forming a first dielectric layer on the first metal layer prior to forming the second metal layer, wherein the first metal layer, the first dielectric layer and the second metal layer form a capacitor, and
wherein, the second temperature is less than the first temperature and the third temperature is less than the second temperature.

2. The method of claim 1 , wherein the first metal layer is formed on a substrate, wherein the first polymer layer is formed between the first metal layer and a periphery of the second metal layer, and wherein the first polymer layer has a thickness in a direction perpendicular to an upper surface of the substrate that is greater than a thickness of the first dielectric layer.

3. The method of claim 2 , wherein the periphery of the second metal layer is spaced farther above the first metal layer than is a center of the second metal layer.

4. The method of claim 3 , wherein the first metal layer is electrically coupled to a gate of a transistor.

5. The method of claim 2 , wherein the first polymer layer is between a first edge of the second metal layer and the first metal layer.

6. The method of claim 1 , wherein the second dielectric layer includes silicon and at least one of oxygen or nitrogen, and wherein the first and second polymer layers are each carbon-based layers.

7. The method of claim 1 , wherein the second metal layer comprises a gate jumper that is coupled between a gate electrode and a gate finger of a transistor.

8. The method of claim 1 , wherein the first metal layer is formed on a substrate, the method further comprising forming a plurality of transistors on the substrate, wherein the dielectric layer is formed on upper surfaces of the transistors and the second polymer layer is not formed on the upper surfaces of the transistors.

9. The method of claim 1 , wherein the first metal layer is formed on a substrate, and wherein the first polymer layer and the second polymer layer are thicker in a direction perpendicular to an upper surface of the substrate than the first dielectric layer.

10. The method of claim 1 , wherein the first temperature is between 200-450° C., the second temperature is between 180-400° C., and the third temperature is between 150-240° C.

11. The method of claim 1 , wherein the electronic circuit comprises a power amplifier integrated circuit chip having a unit cell transistor that includes a channel layer and a barrier layer, wherein the first metal layer comprises a source contact, and wherein the second metal layer comprises a gate jumper that is coupled between a gate electrode and a gate finger of a transistor.

12. The method of claim 1 , wherein the electronic circuit is an internally matched field effect transistor or a ceramic substrate or a printed circuit board that has capacitors and/or inductors formed thereon.

13. The method of claim 1 , wherein the electronic circuit is a packaged electronic circuit.

14. A method of fabricating an electronic circuit, the method comprising:
forming a first polymer layer at a first temperature on a portion of a first metal layer;
forming a second metal layer on the first polymer layer opposite the first metal layer;
forming a dielectric layer at a second temperature on the second metal layer and on the first polymer layer; and
forming a second polymer layer at a third temperature on the dielectric layer, wherein the dielectric layer comprises a second dielectric layer, the method further comprising forming a first dielectric layer on the first metal layer prior to forming the second metal layer, wherein the first metal layer, the first dielectric layer and the second metal layer form a capacitor, and
wherein the second dielectric layer and the second polymer layer are formed on a wafer, the method further comprising dicing the wafer into individual chips after formation of the second dielectric layer and the second polymer layer.

15. A method of fabricating an electronic circuit, the method comprising:
forming a first polymer layer at a first temperature on a portion of a first metal layer;
forming a second metal layer on the first polymer layer opposite the first metal layer;
forming a dielectric layer at a second temperature on the second metal layer and on the first polymer layer, the second temperature being less than the first temperature; and
forming a second polymer layer at a third temperature on the dielectric layer, the third temperature being less than the second temperature,
wherein the first metal layer comprises a metal trace that includes self-coupling sections that have a substantially same instantaneous current direction.

16. A method of fabricating an electronic circuit, the method comprising:
forming a first polymer layer at a first temperature on a portion of a first metal layer;
forming a second metal layer on the first polymer layer opposite the first metal layer;
forming a dielectric layer at a second temperature on the second metal layer and on the first polymer layer; and
forming a second polymer layer at a third temperature on the dielectric layer, wherein the dielectric layer comprises a second dielectric layer, the method further comprising forming a first dielectric layer on the first metal layer prior to forming the second metal layer, wherein the first metal layer, the first dielectric layer and the second metal layer form a capacitor, and
wherein the electronic circuit is a monolithic microwave integrated circuit.

17. A method of fabricating an electronic circuit, the method comprising:
forming a first metal layer on an upper surface of a substrate;
forming a first dielectric layer on an upper surface of the first metal layer;
forming a first polymer layer on the upper surface of the first metal layer and on an upper surface of the first dielectric layer, the first polymer layer having a thickness in a direction perpendicular to the upper surface of the substrate that is greater than a thickness of the first dielectric layer;
forming a second metal layer on the first dielectric layer opposite the first metal layer, wherein the second metal layer extends onto the first polymer layer;
forming a second dielectric layer on the second metal layer and on the first polymer layer; and
forming a second polymer layer on the second dielectric layer,
wherein the first polymer layer is formed between the first metal layer and a periphery of the second metal layer, and
wherein the first metal layer, the first dielectric layer and the second metal layer form a capacitor.

18. The method of claim 17 , wherein the first polymer layer is formed at a first temperature and the second dielectric layer is formed at a second temperature that is lower than the first temperature.

19. The method of claim 18 , wherein the second polymer layer is formed at a third temperature that is lower than the second temperature.

20. The method of claim 17 , further comprising forming a plurality of transistors on the substrate, where

Assignees

• Cree Inc

Inventors

• Bothe Kyle
• Namishia Dan
• Radulescu Fabian
• Sheppard Scott

Classifications

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title