Power transistor with harmonic control

Patent metadata

Field	Value
Publication number	US-10211170-B2
Application number	US-201715674368-A
Country	US
Kind code	B2
Filing date	Aug 10, 2017
Priority date	Aug 24, 2016
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A system and method for a packaged device with harmonic control are presented. In one embodiment, a device includes a substrate and a transistor die coupled to the substrate. The transistor die includes a plurality of transistor cells. Each transistor cell in the plurality of transistor cells includes a control (e.g., gate) terminal. The device includes a second die coupled to the substrate. The second die includes a plurality of individual shunt capacitors coupled between the control terminals of the plurality of transistor cells and a ground reference node. The capacitance values of at least two of the shunt capacitors are significantly different.

First claim

The invention claimed is:

1. A device, comprising:
a substrate;
a transistor die coupled to the substrate, the transistor die including a transistor formed from a plurality of transistor cells, each transistor cell in the plurality of transistor cells including a control terminal; and
a second die coupled to the substrate, the second die including:
a plurality of shunt capacitors, each shunt capacitor in the plurality of shunt capacitors being electrically coupled to the control terminal of a different transistor cell in the plurality of transistor cells, a first shunt capacitor in the plurality of shunt capacitors has a first capacitance value, a second shunt capacitor in the plurality of shunt capacitors has a second capacitance value, and the second capacitance value is at least 5% greater than the first capacitance value.

2. The device of claim 1 , wherein each one of the plurality of shunt capacitors is connected to the control terminal of one of the plurality of transistor cells by one or more wire bonds.

3. The device of claim 2 , wherein the plurality of shunt capacitors are configured to offset variations in resonant frequencies of the plurality of transistor cells resulting from mutual inductances between at least a first set of one or more wire bonds connecting a first shunt capacitor to a first control terminal of a first transistor cell and a second set of one or more wire bonds connecting a second shunt capacitor to a second control terminal of a second transistor cell.

4. The device of claim 1 , wherein the second die further comprises:
a primary capacitor connected to the control terminal of each transistor cell in the plurality of transistor cells, the primary capacitor configured to at least partially determine an input impedance of the device.

5. The device of claim 4 , wherein each transistor cell in the plurality of transistor cells is connected to the primary capacitor in parallel.

6. The device of claim 1 , wherein the plurality of shunt capacitors are configured to filter second order harmonic signals from an input signal to the device.

7. A packaged device, comprising:
a substrate having a ground reference node;
a semiconductor die on the substrate, the semiconductor die including a plurality of transistor cells; and
a plurality of series resonant circuits, each series resonant circuit coupled between one of the plurality of transistor cells and the ground reference node, wherein a first series resonant circuit in the plurality of series resonant circuits resonates at a first resonant frequency, a second series resonant circuit in the plurality of series resonant circuits resonates at a second resonant frequency, and the second resonant frequency is at least 5% greater than the first resonant frequency.

8. The packaged device of claim 7 , wherein each of the shunt capacitors is a metal-oxide-silicon capacitor, MOSCAP, formed on a second substrate.

9. The packaged device of claim 7 , wherein capacitance values of two adjacent shunt capacitors are significantly different, and wherein the capacitance values of the two adjacent shunt capacitors are selected to compensate for an offset variation in resonant frequencies of two adjacent transistor cells to which the two adjacent capacitors are coupled, wherein the offset variation results from mutual inductances between the sets of wire bonds in the two resonant circuits to which the two adjacent transistor cells are coupled.

10. The packaged device of claim 7 , wherein the plurality of series resonant circuits is configured to filter second order harmonic signals from an input signal to the packaged device.

11. The packaged device of claim 7 , including an integrated passive device, IPD, on the substrate, the IPD including the shunt capacitors of the plurality of series resonant circuits.

12. The packaged device of claim 7 , further comprising a primary capacitor coupled to a control terminal of each one of the plurality of transistor cells, and wherein each one of the shunt capacitors also is coupled to a control terminal of each one of the plurality of transistor cells.

13. A method, comprising:
coupling a semiconductor die to a substrate, the semiconductor die including a plurality of transistor cells; and
electrically connecting a shunt capacitor of a plurality of shunt capacitors to each one of the plurality of transistor cells, wherein a first shunt capacitor in the plurality of shunt capacitors has a first capacitance value, a second shunt capacitor in the plurality of shunt capacitors has a second capacitance value, and the second capacitance value is at least 5% greater than the first capacitance value.

14. The method of claim 13 , including coupling a second die to the substrate, wherein the second die includes a primary capacitor and the plurality of shunt capacitors.

15. The method of claim 13 , including connecting a plurality of wire bonds between the plurality of shunt capacitors and the plurality of transistor cells, and wherein the shunt capacitors are configured to offset variations in a resonant frequency of each transistor cell in the plurality of transistor cells resulting from mutual inductances between at least two sets of the plurality of wire bonds.

Assignees

• Nxp Usa Inc

Inventors

• Peyrot Pascal
• Lembeye Olivier
• Mangaonkar Sai Sunil

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/206

  Wires · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title