Assembly of 2XD module using high density interconnect bridges

Patent metadata

Field	Value
Publication number	US-12525562-B2
Application number	US-202318399220-A
Country	US
Kind code	B2
Filing date	Dec 28, 2023
Priority date	Dec 22, 2020
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

First claim

What is claimed is:

1 . A multi-chip module, comprising:
a redistribution layer; a bridge die having a top side and a bottom side, the bottom side on and in contact with the redistribution layer, and the bridge die having and a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall, and the bridge die having bridge pads on the top side, and solder on the bridge pads, wherein the bridge die has a plurality of through silicon vias (TSVs) therein; a mold layer on and in contact with the redistribution layer and laterally adjacent to the first sidewall and the second sidewall of the bridge die, the mold layer having a bottommost surface at a same level as the bottom side of the bridge die; first conductive pillars in the mold layer and laterally spaced apart from the first sidewall of the bridge die, the first conductive pillars having an uppermost surface above an uppermost surface of the bridge pads of the bridge die, and the first conductive pillars electrically coupled to the redistribution layer; second conductive pillars in the mold layer and laterally spaced apart from the second sidewall of the bridge die, the second conductive pillars having an uppermost surface above the uppermost surface of the bridge pads of the bridge die, and the second conductive pillars electrically coupled to the redistribution layer; a first die over the bridge die and over the first conductive pillars, the first die coupled to the first conductive pillars and to a first portion of the bridge pads of the bridge die; a second die over the bridge die and over the second conductive pillars, the second die laterally spaced apart from the first die, and the second die coupled to the second conductive pillars and to a second portion of the bridge pads of the bridge die, the redistribution layer extending laterally beyond an outer side of the first die and an outer side of the second die, wherein the mold layer has an uppermost surface at most as high as an uppermost surface of the first die and the second die; and a plurality of solder balls beneath and coupled to the redistribution layer, the plurality of solder balls beneath the first conductive pillars, beneath the bridge die, and beneath the second conductive pillars.

2 . The multi-chip module of claim 1 , wherein the mold layer is in direct contact with the first sidewall and the second sidewall of the bridge die.

3 . The multi-chip module of claim 1 , wherein the mold layer has an uppermost surface above the top side of the bridge die.

4 . The multi-chip module of claim 1 , wherein the uppermost surface of the mold layer is at a same level as an uppermost surface of the first die and at a same level as an uppermost surface of the second die.

5 . The multi-chip module of claim 1 , wherein the redistribution layer has an edge in vertical alignment with an edge of the mold layer.

6 . The multi-chip module of claim 5 , wherein the redistribution layer has a second edge in vertical alignment with a second edge of the mold layer, the second edge of the redistribution layer laterally opposite the edge of the redistribution layer, and the second edge of the mold layer laterally opposite the edge of the mold layer.

7 . The multi-chip module of claim 1 , wherein a portion of the plurality of solder balls is outside of a footprint of the first die and the second die.

8 . A multi-chip module, comprising:
a layer for pitch spreading and integration; a first die on and in contact with the layer for pitch spreading and integration, the first die having a first bridge pad and a second bridge pad, and solder on the first bridge pad and the second bridge pad, wherein the first die has a plurality of through silicon vias (TSVs) therein; a mold layer on and in contact with the layer for pitch spreading and integration and laterally adjacent to a first sidewall and a second sidewall of the first die, the mold layer having a bottommost surface at a same level as the bottom side of the first die; a first conductive pillar in the mold layer and laterally spaced apart from the first sidewall of the first die, the first conductive pillar having an uppermost surface above an uppermost surface of the first bridge pad and the second bridge pad, and the first conductive pillar electrically coupled to the layer for pitch spreading and integration; a second conductive pillar in the mold layer and laterally spaced apart from the second sidewall of the first die, the second conductive pillar having an uppermost surface above the uppermost surface of the first bridge pad and the second bridge pad, and the second conductive pillar electrically coupled to the layer for pitch spreading and integration; a second die over the first die and over the first conductive pillar, the second die coupled to the first conductive pillar and to the first bridge pad; a third die over the first die and over the second conductive pillar, the third die laterally spaced apart from the first die, and the third die coupled to the second conductive pillar and to the second bridge pad, the layer for pitch spreading and integration extending laterally beyond an outer side of the second die and an outer side of the third die, wherein the mold layer has an uppermost surface at most as high as an uppermost surface of the second die and the third die; and a first solder ball beneath the first conductive pillar, a second solder ball beneath the first die, and a third solder ball beneath the second conductive pillar.

9 . The multi-chip module of claim 8 , wherein the mold layer is in direct contact with the first sidewall and the second sidewall of the first die.

10 . The multi-chip module of claim 8 , wherein the mold layer has an uppermost surface above the top side of the first die.

11 . The multi-chip module of claim 8 , wherein the uppermost surface of the mold layer is at a same level as an uppermost surface of the second die and at a same level as an uppermost surface of the third die.

12 . The multi-chip module of claim 8 , wherein the layer for pitch spreading and integration has a first edge in vertical alignment with a first edge of the mold layer, and wherein the layer for pitch spreading and integration has a second edge in vertical alignment with a second edge of the mold layer, the second edge of the layer for pitch spreading and integration laterally opposite the first edge of the layer for pitch spreading and integration, and the second edge of the mold layer laterally opposite the first edge of the mold layer.

13 . The multi-chip module of claim 8 , further comprising a fourth solder ball outside of a footprint of the second die and the third die.

14 . A multi-chip module, comprising:
a redistribution layer; a bridge die having a top side and a bottom side, the bottom side on and in contact with the redistribution layer, and the bridge die having and a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall, and the bridge die having bridge pads on the top side, and solder on the bridge pads, wherein the bridge die has a plurality of through silicon vias (TSVs) therein; a mold layer on and in contact with the redistribution layer and laterally adjacent to the first sidewall and the second sidewall of the bridge die, the mold layer having a bottommost surface at a same level as the bottom side of the bridge die; conductive pillars in the mold layer and laterally spaced apart from the first sidewall of the bridge die and laterally spaced apart from the second si

Assignees

• Intel Corp

Inventors

• Waidhas Bernd
• Wolter Andreas
• Seidemann Georg
• Wagner Thomas

Classifications

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65 Primary

  Shapes or dispositions of interconnections · CPC title