Integration process for fabricating embedded memory

Patent metadata

Field	Value
Publication number	US-12525543-B1
Application number	US-202117449796-A
Country	US
Kind code	B1
Filing date	Oct 1, 2021
Priority date	Oct 1, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

First claim

What is claimed is:

1 . A method of fabricating a device structure, the method comprising:
forming a first conductive interconnect in a dielectric in a memory region and a second conductive interconnect in a logic region; depositing an etch stop layer on the dielectric and on the first conductive interconnect and on the second conductive interconnect; forming an electrode structure on the first conductive interconnect by etching an opening in the etch stop layer and depositing a first conductive material; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack, wherein the electrode structure is wider than the memory device and etching the material layer stack further comprises recessing portions of the electrode structure not under the memory device, and wherein the recessing forms a first surface of the electrode structure adjacent the memory device that is below an uppermost surface of the electrode structure; forming a spacer on a sidewall of the memory device by depositing an encapsulation layer and etching the encapsulation layer; depositing a dielectric layer on the memory device; forming a via electrode on the memory device by forming a first opening in the dielectric layer and depositing a second conductive material in the first opening; and forming a via structure on the second conductive interconnect and a metal line on the via structure by patterning a second opening in the dielectric layer and in the etch stop layer.

2 . The method of claim 1 , wherein depositing the material layer stack comprises depositing at least two layers comprising the ferroelectric material, and wherein the ferroelectric material comprises one of:
bismuth ferrite (BFO) or BFO with a first doping material where in the first doping material is one of lanthanum or elements from lanthanide series of periodic table; lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb; a relaxor ferroelectric material which includes one of; lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or Barium titanium-barium strontium titanium (BT-BST); a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ; a hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); and
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides; hafnium oxides such as Hf (1-x) E x O y , where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y; Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-x-y) Mg (x) Nb (y) N, y doped HfO 2 , where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction;
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100,
wherein the paraelectric material comprises: SrTiO 3 , Ba (x) Sr (y) TiO 3 (where x is −0.05, and y is 0.95), HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or a PMN-PT based relaxor ferroelectric.

3 . The method of claim 2 , wherein etching the material layer stack to form the memory device comprises utilizing a reactive ion etching process, and wherein the reactive ion etching process forms the memory device having sidewalls that are tapered relative to a lowermost surface of the memory device.

4 . The method of claim 3 , wherein the reactive ion etching process etches layers within the material layer stack, and wherein a respective layer in the layers each comprise a respective sidewall with a different slope.

5 . The method of claim 2 , wherein etching the material layer stack to form the memory device comprises utilizing a reactive ion etching process, and wherein the reactive ion etching process is selective to the etch stop layer.

6 . The method of claim 1 , wherein forming the spacer further comprises depositing the encapsulation layer on the first surface and below an interface between the memory device and the electrode structure.

7 . The method of claim 1 , wherein forming the spacer further comprises depositing the encapsulation layer on the first surface wherein the first surface is curved.

8 . The method of claim 7 , wherein etching the encapsulation layer further comprises recessing a portion of the etch stop layer is below the uppermost surface of the electrode structure.

9 . The method of claim 1 , wherein the electrode structure is wider than the first conductive interconnect, and wherein etching the opening in the etch stop layer comprises recessing a portion of the dielectric adjacent to the first conductive interconnect and depositing the first conductive material on a sidewall of the first conductive interconnect.

10 . The method of claim 6 , wherein etching the material layer stack to form the memory device comprises utilizing a reactive ion etching process, and wherein the reactive ion etching process forms the memory device having sidewalls that are vertical relative to a lowermost surface of the memory device.

11 . The method of claim 10 , wherein the spacer is conformal to the sidewalls that are vertical.

12 . The method of claim 10 , wherein the first surface is planar, and wherein the electrode structure comprises a vertical sidewall, and wherein the spacer extends onto the vertical sidewall.

13 . The method of claim 1 , wherein the first surface is sloped, the spacer comprises a lowermost portion that is on the first surface, and wherein the spacer comprises a non-uniform lateral thickness relative to the sidewalls that are vertical.

14 . The method of claim 3 , wherein the spacer formed by etching the encapsulation layer is conformal to the sidewalls that are tapered.

15 . The method of claim 3 , wherein forming the spacer comprises using a physical vapor deposition process to deposit the encapsulation layer, and wherein etching the encapsulation layer further comprises forming the spacer comprising a wider top portion adjacent to an uppermost surface of the memory device and a narrower portion adjacent to the electrode structure.

16 . The method of claim 8 , wherein etching the encapsulation layer further comprises recessing the etch stop layer to a level of the first surface.

17 . The method of claim 1 , wherein the memory device further comprises a hardmask, wherein the hardmask comprises dual layers comprising a second dielectric layer on a conductive layer, and wherein the via electrode extends through the second dielectric layer and is in contact with an uppermost surface of the conductive layer.

Assignees

• Kepler Computing Inc

Inventors

• Sato Noriyuki
• Guhabiswas Debraj
• Gosavi Tanay
• Mukherjee Niloy
• Mathuriya Amrita
• Manipatruni Sasikanth

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title