Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12525533-B2
Application number	US-202217731464-A
Country	US
Kind code	B2
Filing date	Apr 28, 2022
Priority date	Sep 17, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

A semiconductor device includes: a standard cell array including a plurality of standard cells, each of the plurality of standard cells; a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction; a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array, the capacitor structure having vias connecting the electrode structures; and contacts electrically connecting the capacitor structure and the standard cell array to each other. Each of the plurality of standard cells provides a unit capacitor circuit having capacitance that is based on a connection structure of active regions and gates of first and second transistors thereof.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a standard cell array including a first plurality of standard cells and a second plurality of standard cells; a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction; a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array, and the capacitor structure further having vias connecting the electrode structures; and contacts electrically connecting the capacitor structure and the standard cell array to each other, wherein: each of the first plurality of standard cells includes a first transistor connected to a first power supply line of the plurality of power supply lines, and a second transistor connected to a second power supply line of the plurality of power supply lines, and each of the first plurality of standard cells configured to provide a unit capacitor circuit having a capacitance that is based on a connection structure of (i) active regions of the first and second transistors thereof and the first and second power supply lines and (ii) gates of the first and second transistors thereof and the first and second power supply lines, for each of the first plurality of standard cells, the first power supply line is configured to provide a first power supply voltage and is connected to a first active region of the first transistor thereof, the second power supply line is configured to provide a second power supply voltage that is connected to a first active region of the second transistor thereof, the connection structure of the gates of the first and second transistors and the first and second power supply lines of a first set of the first plurality of standard cells is different from the connection structure of the gates of the first and second transistors and the first and second power supply lines of a second set of the first plurality of standard cells, a first voltage level of the gates of the first transistors of the first set of the first plurality of standard cell and a second voltage level of the gates of the first transistors of the second set of the first plurality of standard cells are different each other, the second plurality of standard cells has a different connection structure from the first plurality of standard cells and includes a fourth standard cell, a third transistor of the fourth standard cell is connected to a third power supply line of the plurality of power supply lines, and a fourth transistor of the fourth standard cell is connected to the third power supply line and includes impurities having a conductivity type that is different from a conductivity type of the third transistor of the fourth standard cell, and in the fourth standard cell, the third power supply line is configured to provide the first power supply voltage and is connected to the active regions and gates of the third and fourth transistors.

2 . The semiconductor device of claim 1 , wherein the first set of the first plurality of standard cells includes a first standard cell, and wherein:
the second power supply voltage is lower than the first power supply voltage, the gate of the first transistor of the first standard cell is connected to the second power supply line, and the gate of the second transistor of the first standard cell is connected to the first power supply line.

3 . The semiconductor device of claim 1 , wherein the first set of the first plurality of standard cells includes a second standard cell, and wherein:
the second power supply voltage is lower than the first power supply voltage, and the gates of the first and second transistors of the second standard cell are connected to each other.

4 . The semiconductor device of claim 3 , wherein:
the gates of the first and second transistors of the second standard cell are floated.

5 . The semiconductor device of claim 1 , wherein:
the first set of the first plurality of standard cells includes a third standard cell in which the first power supply line is configured to provide the first power supply voltage and is connected to a drain region of the first transistor of the third standard cell, the second power supply line is configured to provide the second power supply voltage that is lower than the first power supply voltage and is connected to a source region of the second transistor of the third standard cell, the gate of the first transistor of the third standard cell is connected to a drain region of the second transistor of the third standard cell through an interconnection pattern, and a source region of the first transistor of the third standard cell is connected to the gate of the second transistor of the third standard cell.

6 . The semiconductor device of claim 1 , wherein:
the fourth standard cell includes a gate structure that provides the gate of the third transistor and the gate of the fourth transistor; and the gate structure extends in a second direction that intersects the first direction.

7 . The semiconductor device of claim 1 , wherein the first set of the first plurality of standard cells includes a fifth standard cell, and wherein:
the second power supply voltage is higher than the first power supply voltage, and the second power supply line is connected to the active region of the second transistor of the fifth standard cell; and the fifth standard cell comprises:
a third power supply line configured to provide the second power supply voltage to the gate of the first transistor of the fifth standard cell; and
a fourth power supply line configured to provide the first power supply voltage to the gate of the second transistor of the fifth standard cell.

8 . The semiconductor device of claim 7 , wherein:
in the fifth standard cell, the first transistor is a NMOS transistor and the second transistor is a PMOS transistor.

9 . The semiconductor device of claim 1 , wherein the first set of the first plurality of standard cells includes a sixth standard cell, and wherein:
the gates of the first and second transistors of the sixth standard cell are connected to each other, and the first and second transistors include impurities having the same conductivity type.

10 . The semiconductor device of claim 9 , wherein:
the gates of the first and second transistors of the sixth standard cell are floated.

11 . The semiconductor device of claim 9 , further comprising:
a third power supply line connected to the gates of the first and second transistors of the sixth standard cell and configured to provide the second power supply voltage that is lower than the first power supply voltage.

12 . The semiconductor device of claim 9 , further comprising:
a third power supply line connected to the gates of the first and second transistors of the sixth standard cell and configured to provide the second power supply voltage that is higher than the first power supply voltage.

13 . The semiconductor device of claim 1 , wherein:
the electrode structures included in the capacitor structure include electrode structures having opposite polarities; and at least portions of the electrode structures having opposite polarities vertically overlap.

14 . A semiconductor device comprising:
a standard cell array including a plurality of standard cells; a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction; a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array and vias connecting the electrode

Assignees

• Samsung Electronics Co Ltd

Inventors

• YU Jisu
• Do Youngsook
• Seo Eunsung
• Kim Wooseok
• Yu Wonsik
• Jeong Chanyoung

Classifications

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/432

  comprising crossing interconnections · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title