Method and apparatus for filling a gap

Patent metadata

Field	Value
Publication number	US-12525449-B2
Application number	US-202318117729-A
Country	US
Kind code	B2
Filing date	Mar 6, 2023
Priority date	Jul 28, 2016
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a sub saturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

First claim

The invention claimed is:

1 . A semiconductor processing apparatus comprising:
one or more reaction chambers for accommodating a substrate provided with gaps created during manufacturing of a feature on the substrate; a first source for a first reactant in gas communication via a first valve with one of the reaction chambers; a second source for a second reactant in gas communication via a second valve with one of the reaction chambers; and a third source for a third reactant, in gas communication via a third valve with one of the reaction chambers; wherein the apparatus comprises a controller operably connected to the first, second and third gas valves and configured and programmed to control: introducing with the first valve a subsaturating first dose; introducing with the second valve a saturating second dose; and introducing with the third valve a third reactant to the substrate with a third dose, wherein the second reactant is a relatively high growth rate reactant in reaction with the third reactant; wherein the second reactant is substantially blocked by the first reactant, and wherein the first reactant is introduced with a subsaturating first dose reaching a top area of the surface of the gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the gaps.

2 . The semiconductor processing apparatus of claim 1 , wherein the third source comprises H 2 O, O 2 , ozone, N 2 , H 2 , hydrazine, or ammonia.

3 . The semiconductor processing apparatus of claim 1 , wherein the controller is further configured and programmed to control: removing excess reactant and byproduct from the reaction chamber after each step of introducing a first, second and third reactant.

4 . The semiconductor processing apparatus of claim 1 , wherein the controller is further configured and programmed to control repeating:
introducing with the first valve the sub saturating first dose; introducing with the second valve the saturating second dose; and introducing with the third valve the third reactant to the substrate to fill the gaps.

5 . The semiconductor processing apparatus of claim 1 , wherein the third reactant comprises nitrogen, hydrogen, hydrazine, and/or ammonia.

6 . A semiconductor processing apparatus comprising:
one or more reaction chambers for accommodating a substrate provided with gaps created during manufacturing of a feature on the substrate; a first source for a first reactant in gas communication via a first valve with one of the reaction chambers; a second source for a second reactant in gas communication via a second valve with one of the reaction chambers; and a third source for a third reactant, in gas communication via a third valve with one of the reaction chambers; wherein the apparatus comprises a controller operably connected to the first, second and third gas valves and configured and programmed to control: introducing with the first valve a subsaturating first dose; introducing with the second valve a saturating second dose; and introducing with the third valve a third reactant to the substrate with a third dose, wherein the second reactant is a relatively high growth rate reactant in reaction with the third reactant; wherein the first reactant is a low growth rate reactant in reaction with the third reactant.

7 . The semiconductor processing apparatus of claim 6 , wherein the low growth rate reactant comprises a silane.

8 . The semiconductor processing apparatus of claim 7 , wherein the low growth rate reactant comprises one or more reactants of a group of reactants comprising diiodomethylsilane, methoxy(dimethyl)octylsilane, alkylchlorosilanes, alkylalkoxysilanes, and alkylaminosilanes.

9 . A semiconductor processing apparatus comprising:
one or more reaction chambers for accommodating a substrate provided with gaps created during manufacturing of a feature on the substrate; a first source for a first reactant in gas communication via a first valve with one of the reaction chambers; a second source for a second reactant in gas communication via a second valve with one of the reaction chambers; and a third source for a third reactant, in gas communication via a third valve with one of the reaction chambers; wherein the apparatus comprises a controller operably connected to the first, second and third gas valves and configured and programmed to control: introducing with the first valve a subsaturating first dose; introducing with the second valve a saturating second dose; and introducing with the third valve a third reactant to the substrate with a third dose, wherein the second reactant is a relatively high growth rate reactant in reaction with the third reactant; wherein the first reactant is a relatively no growth reactant whereby the first reactant is substantially removed from the surface in reaction with the third reactant.

10 . The semiconductor processing apparatus of claim 9 , wherein the relatively no growth reactant is an etch sensitive reactant and the third reactant causes etching of the first reactant so as to remove the first reactant from the surface.

11 . The semiconductor processing apparatus of claim 10 , wherein the first reactant comprises fluorine.

12 . The semiconductor processing apparatus of claim 11 , wherein the third reactant creates a plasma which removes fluorine from the etch sensitive reactant creating a fluorine plasma etching away the first reactant.

13 . The semiconductor processing apparatus of claim 10 , wherein the etch sensitive reactant comprises trimethoxy (3,3,3-tri-fluoropropyl) silane.

14 . The semiconductor processing apparatus of claim 10 , wherein the etch sensitive reactant comprises an amine group.

15 . The semiconductor processing apparatus of claim 10 , wherein the etch sensitive reactant comprises a di-isopropyl-amine group.

16 . The semiconductor processing apparatus of claim 10 , wherein the etch sensitive reactant comprises an alkane group.

17 . The semiconductor processing apparatus of claim 10 , wherein the etch sensitive reactant comprises octane.

Assignees

• Asm Ip Holding Bv

Inventors

• Pore Viljami
• Knaepen Werner
• Jongbloed Bert
• Pierreux Dieter
• Van Aerde Steven R A
• Haukka Suvi
• Fukazawa Atsuki
• Fukuda Hideaki

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69393

  the material containing tantalum, e.g. Ta2O5 · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6687

  the compound comprising silicon and nitrogen · CPC title