Method and apparatus to reduce feature charging in plasma processing chamber

Patent metadata

Field	Value
Publication number	US-12525433-B2
Application number	US-202117352176-A
Country	US
Kind code	B2
Filing date	Jun 18, 2021
Priority date	Jun 9, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

Embodiments provided herein include an apparatus and methods for the plasma processing of a substrate in a processing chamber. In some embodiments, aspects of the apparatus and methods are directed to reducing defectivity in features formed on the surface of the substrate, improving plasma etch rate, and increasing selectivity of etching material to mask and/or etching material to stop layer. In some embodiments, the apparatus and methods enable processes that can be used to prevent or reduce the effect of trapped charges, disposed within features formed on a substrate, on the etch rate and defect formation. In some embodiments, the plasma processing methods include the synchronization of the delivery of pulsed-voltage (PV) waveforms, and alternately the delivery of a PV waveform and a radio frequency (RF) waveform, so as to allow for the independent control of generation of electrons that are provided, during one or more stages of a PV waveform cycle, to neutralize the trapped charges formed in the features formed on the substrate.

First claim

What is claimed is:

1 . A processing method, comprising:
establishing, by use of a first waveform generator, a first DC pulse voltage waveform at a bias electrode disposed in an electrostatic chuck of a substrate support assembly, wherein
the first DC pulse voltage waveform having a pulse frequency, the first pulse voltage waveform comprises:
a first stage; and
a second stage that has a lower voltage level than a voltage level in the first stage,

the electrostatic chuck having a body formed of a dielectric material, the body comprising:
a substrate supporting surface; and
the bias electrode disposed in the dielectric material of the body; and

establishing, by use of a RF waveform generator, an RF waveform at a first electrode disposed over the substrate support assembly, wherein
the RF waveform comprises a sinusoidal waveform having an RF frequency, and
the first pulse voltage waveform and the RF waveform are synchronized wherein the RF frequency matches the pulse frequency, so that
a trough of the RF waveform is formed during a period of time when the first stage of the first pulse voltage waveform is established at the bias electrode, and
a peak of the RF waveform is formed during a period of time when the second stage of the first pulse voltage waveform is established at the bias electrode.

2 . The processing method of claim 1 , further comprising:
establishing, by use of a second waveform generator, a second pulse voltage waveform at a second electrode disposed in the substrate support assembly, wherein
the second pulse voltage waveform comprises:
a first stage; and
a second stage that has a lower voltage level than a voltage level in the first stage.

3 . The processing method of claim 2 , wherein
the first stage of the first pulse voltage waveform and the first stage of the second pulse voltage waveform are simultaneously established, and the second stage of the first pulse voltage waveform and the second stage of the second pulse voltage waveform are simultaneously established.

4 . The processing method of claim 1 , wherein the first pulse voltage waveform and the RF waveform have a frequency that is less than about 1 MHz.

5 . The processing method of claim 1 , wherein the voltage level in the peak of the RF waveform is configured to generate secondary electrons from a surface of the first electrode, and the first electrode comprises silicon.

6 . The processing method of claim 5 , wherein the voltage level in the peak of the RF waveform is configured to cause ions to bombard a surface of the first electrode, and generate secondary electrons which can gain energies up to 3 keV to become highly directional towards the substrate surface.

Assignees

• Applied Materials Inc

Inventors

• Cui Linying
• Rogers James
• Dhindsa Rajinder
• Ramaswamy Kartik

Classifications

• H10P72/722

  Details of electrostatic chucks · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01J37/32137

  controlling of the discharge by modulation of energy · CPC title

• H01J37/32174 Primary

  Circuits specially adapted for controlling the RF discharge · CPC title

• H01J37/32128 Primary

  using particular waveforms, e.g. polarised waves · CPC title