Transistor, method for manufacturing same, and ternary inverter comprising same

Patent metadata

Field	Value
Publication number	US-12520539-B2
Application number	US-202017636328-A
Country	US
Kind code	B2
Filing date	Nov 19, 2020
Priority date	Nov 19, 2019
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A transistor includes: a substrate; a constant current formation layer provided on the substrate; a pair of source/drain patterns provided on the constant current formation layer; a gate electrode provided between the pair of source/drain patterns; a channel pattern extending in a direction between the pair of source/drain patterns; and a gate insulating layer surrounding the channel pattern, wherein the channel pattern penetrates the gate insulating layer and the gate electrode and is electrically connected to the source pattern and the drain pattern, the gate insulating layer separates the channel pattern and the gate electrode from each other, the constant current formation layer generates a constant current between the drain pattern and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

First claim

What is claimed is:

1 . A transistor comprising:
a substrate; a constant current formation layer disposed on the substrate in direct contact with the substrate; a pair of source/drain patterns disposed on the constant current formation layer in direct contact with the constant current formation layer; a gate electrode provided between the pair of source/drain patterns; a channel pattern extending in a direction between the pair of source/drain patterns; and a gate insulating layer surrounding the channel pattern, wherein the channel pattern penetrates the gate insulating layer and the gate electrode and is electrically connected to the source pattern and the drain pattern, the gate insulating layer separates the channel pattern and the gate electrode from each other, the constant current formation layer generates a constant current between the drain pattern and the substrate, the constant current being a band to band tunneling current that flows from the substrate through the constant formation layer to the drain, or from the drain through the constant current formation layer to the substrate, the constant current is independent from a gate voltage applied to the gate electrode, wherein an electric field is formed between the constant current formation layer and the pair of source/drain patterns, and an intensity of the electric field is greater than or equal to about 10 6 V/cm.

2 . The transistor of claim 1 , wherein the constant current formation layer has a first conductive type,
the pair of source/drain patterns have a second conductive type that is different from the first conductive type, and a doping concentration of the constant current formation layer is greater than or equal to about 3×10 18 cm −3 .

3 . The transistor of claim 1 , wherein the gate insulating layer extends between the gate electrode and the pair of source/drain patterns and separates the gate electrode from the pair of source/drain patterns.

4 . The transistor of claim 1 , further comprising a pair of gate spacers provided on both side surfaces of the gate electrode,
wherein the pair of gate spacers are provided between the pair of source/drain patterns and the gate electrode and electrically disconnect the pair of source/drain patterns from the gate electrode.

5 . The transistor of claim 4 , further comprising the gate insulating layer extends between the gate electrode and the pair of gate spacers and separating the gate electrode from the pair of gate spacers.

6 . The transistor of claim 1 , wherein the channel pattern is provided in a multiple number, and
the plurality of channel patterns are apart from each other in a direction perpendicular to an upper surface of the constant current formation layer.

7 . The transistor of claim 6 , wherein the gate insulating layer is provided between the plurality of channel patterns and the gate electrode and separates the plurality of channel patterns from the gate electrode.

Assignees

• Ulsan Nat Inst Science & Tech Unist

Inventors

• Kim Kyung Rok
• Chang Ji Won
• Jeong Jae Won
• Choi Youngeun
• Kim Wooseok

Classifications

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title