Ternary digit logic circuit

Patent metadata

Field	Value
Publication number	US-10133550-B2
Application number	US-201515563473-A
Country	US
Kind code	B2
Filing date	Dec 29, 2015
Priority date	Jul 10, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A ternary logic circuit according to the present invention includes a pull-up device ( 100 ) and a pull-down device ( 200 ) connected in series between power voltage sources (V DD and GND), and an input voltage (V IN ) source and output voltage (V OUT ) source. When both the pull-up device ( 100 ) and the pull-down device ( 200 ) are turned off by an input voltage (V IN ), both the pull-up device ( 100 ) and the pull-down device ( 200 ) operate as simple resistors which are affected only by an output voltage (V OUT ) and form a ternary digit (“1” state) through voltage division. When only one of the pull-up device ( 100 ) or the pull-down device ( 200 ) is turned on to allow a current to flow therethrough, V DD (“2” state) or GND (“0” state) is output as the output voltage (V OUT ). Accordingly, a bit density can be remarkably increased.

First claim

The invention claimed is:

1. A ternary logic circuit comprising:
a pull-up device ( 100 ) and a pull-down device ( 200 ) connected in series between power voltage sources (V DD and GND); and
an input voltage (V IN ) source and an output voltage (V OUT ) source,
wherein, when both the pull-up device ( 100 ) and the pull-down device ( 200 ) are turned off by an input voltage (V IN ), both the pull-up device ( 100 ) and the pull-down device ( 200 ) operate as simple resistors which are affected only by an output voltage (V OUT ) and form a ternary digit (“1” state) through voltage division, and
when only one of the pull-up device ( 100 ) or the pull-down device ( 200 ) is turned on to allow a current to flow therethrough, V DD (“2” state) or GND (“0” state) is transferred as the output voltage (V OUT ),
wherein the ternary logic circuit has a current (I CON ) component, which is not affected by the input voltage (V IN ) and is affected only by the output voltage (V OUT ), and a current (I EXT ) component, which is affected by the input voltage (V IN ) and is not affected by the output voltage (V OUT ),
the current (I CON ), which is affected by the output voltage (V OUT ), is realized via a junction BTBT current (I BTBT ) independent of a gate voltage,
the current (I EXT ), which is affected by the input voltage (V IN ), is realized via a subthreshold current (I sub ), and
characteristics of the BTBT current (I BTBT ) and the subthreshold current (I sub ) are obtained by a simple increase in a channel doping in a binary inverter, so that the binary inverter operates as a ternary inverter.

2. The ternary logic circuit of claim 1 , wherein
the current (I CON ), which is affected by the output voltage (V OUT ), has a current value I C when the output voltage (V OUT ) is half of an operating voltage (V DD ), that is, (I CON )=I C when V OUT =V DD /2, and
the current (I EXT ), which is affected by the input voltage (V IN ), has a current value I E when the input voltage (V IN ) is half of the operating voltage (V DD ), that is (I EXT )=I E when V IN =V DD /2, and exponentially increases to a maximum current (I MAX ) at a point where the input voltage (V IN ) and the operating voltage (V DD ) are equal to each other, that is, when V IN =V DD .

3. The ternary logic circuit of claim 2 , wherein a current output from the pull-up device ( 100 ) and the pull-down device ( 200 ) is calculated by the following equation:

I
OUT

⁡

(

V
IN

,

V
OUT

)

=

⁢

I
CON

⁡

(

V
OUT

)

+

I
EXP

⁡

(

V
IN

)

,

=

⁢

I
C

⁢

exp
⁡

[

±

α
⁡

(

V
OUT

-

V
DD

2

)

]

+

I
E

⁢

exp
⁡

[

±

β
⁡

(

V
IN

-

V
DD

2

)

]

wherein, in the equation, α and β are exponential coefficients of each current mechanism, and + and − signs before α and β are respectively signs applied to the pull-down device ( 200 ) and the pull-up device ( 100 ).

Assignees

• Ulsan Nat Inst Science & Tech Unist

Inventors

• Kim Kyung Rok
• Shin Sun Hae
• Jang E San
• Jeong Jae Won

Classifications

• H03K19/09429

  one of the states being the high impedance or floating state · CPC title

• G06F7/48 Primary

  using non-contact-making devices, e.g. tube, solid state device; using unspecified devices · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title

• H03K19/00315

  in field-effect transistor circuits · CPC title