Three-dimensional memory device and fabrication method for improved yield and reliability

Patent metadata

Field	Value
Publication number	US-12520488-B2
Application number	US-202218082080-A
Country	US
Kind code	B2
Filing date	Dec 15, 2022
Priority date	Nov 25, 2022
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure.

First claim

What is claimed is:

1 . A three-dimensional (3D) memory device, comprising:
a conductor/insulator stack including a conductive layer and a dielectric layer alternatingly stacked; a plurality of channel hole structures in a first region of memory cells in the conductor/insulator stack; a gate line slit (GLS) structure adjacent to the first region, through the conductor/insulator stack, and extending along a first direction; a blocking structure adjacent to the first region, through the conductor/insulator stack, and extending along a second direction, the first and second directions being perpendicular; and a first dummy channel hole structure in the first region, the first dummy channel hole structure extending through the conductor/insulator stack, being adjacent to the blocking structure, and including one or more dielectric materials that fill a channel hole to form a first dielectric filling structure.

2 . The 3D memory device according to claim 1 , wherein the first dielectric filling structure extends through the conductor/insulator stack.

3 . The 3D memory device according to claim 1 , wherein the conductor/insulator stack includes a first conductor/insulator stack and a second conductor/insulator stack, the first conductor/insulator stack is between a semiconductor layer and the second conductor/insulator stack, and the first dielectric filling structure extends through the first conductor/insulator stack.

4 . The 3D memory device according to claim 3 , wherein the first dummy channel hole structure includes one of the plurality of channel hole structures extending through the second conductor/insulator stack.

5 . The 3D memory device according to claim 1 , further comprising:
a second dummy channel hole structure in a second region separated from the first region by the blocking structure, the second dummy channel hole structure extending through the conductor/insulator stack, being adjacent to the blocking structure, and separated from the first dummy channel hole structure by the blocking structure.

6 . The 3D memory device according to claim 5 , wherein the second dummy channel hole structure includes a second dielectric filling structure extending through the conductor/insulator stack.

7 . The 3D memory device according to claim 1 , wherein each channel hole structure comprises:
a functional layer including a blocking layer, a charge trap layer, and/or a tunneling layer; and a semiconductor channel formed over the functional layer.

8 . A three-dimensional (3D) memory device, comprising:
a conductor/insulator stack including a conductive layer and a dielectric layer alternatingly stacked; a plurality of channel hole structures in a first region of memory cells in the conductor/insulator stack; a gate line slit (GLS) structure adjacent to the first region and extending along a first direction; a blocking structure separating the first region and a second region and extending along a second direction, the first and second directions being perpendicular; and a first dummy channel hole structure in the first region, the first dummy channel hole structure including one or more dielectric materials that fill a channel hole to form a first dielectric filling structure.

9 . The 3D memory device according to claim 8 , wherein the first dummy channel hole structure is adjacent to the blocking structure.

10 . The 3D memory device according to claim 8 , wherein the first dielectric filling structure extends through the conductor/insulator stack.

11 . The 3D memory device according to claim 8 , wherein the conductor/insulator stack includes a first conductor/insulator stack and a second conductor/insulator stack formed over the first conductor/insulator stack, and the first dielectric filling structure extends through the first conductor/insulator stack.

12 . The 3D memory device according to claim 8 , further comprising:
a second dummy channel hole structure in the second region, the second dummy channel hole structure extending through the conductor/insulator stack, being adjacent to the blocking structure, and separated from the first dummy channel hole structure by the blocking structure.

13 . The 3D memory device according to claim 12 , wherein the second dummy channel hole structure includes a second dielectric filling structure extending through the conductor/insulator stack.

14 . The 3D memory device according to claim 8 , wherein each channel hole structure comprises:
a functional layer including a blocking layer, a charge trap layer, and/or a tunneling layer; and a semiconductor channel formed over the functional layer.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Kun
• Zhou Wenxi
• Wu Linchun
• Han Yuhui
• Sun Changzhi
• Xia Zhiliang
• Huo Zongliang

Classifications

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/697

  having trapping at multiple separated sites, e.g. multi-particles trapping sites · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title