Memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12520486-B2
Application number	US-202218090931-A
Country	US
Kind code	B2
Filing date	Dec 29, 2022
Priority date	Dec 26, 2022
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a peripheral circuit bonded to the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; plate lines extending in the second direction; and a first dielectric layer disposed between the semiconductor body and the word line and the plate line.

First claim

What is claimed is:

1 . A memory device, comprising:
an array of memory cells disposed on a first side of a first semiconductor layer, wherein each of the memory cells comprises:
a semiconductor body extending in a first direction, wherein a first terminal and a second terminal are formed at both ends of the semiconductor body;
a word line extending in a second direction perpendicular to the first direction;
plate lines extending in the second direction; and
a first dielectric layer disposed between the semiconductor body and the word line and the plate line; and
a peripheral circuit bonded to the array of memory cells.

2 . The memory device of claim 1 , wherein the peripheral circuit is boned to a second side of the first semiconductor layer.

3 . The memory device of claim 2 , further comprising:
a contact structure extending in the first direction, penetrating the first semiconductor layer, and connecting a pad-out structure and the peripheral circuit.

4 . The memory device of claim 3 , wherein the pad-out structure is disposed above the array of memory cells.

5 . The memory device of claim 1 , wherein each of the memory cells comprises:
a second dielectric layer disposed between plate lines and extending in the second direction, wherein the semiconductor body penetrates the second dielectric layer, the word line, and the plate lines in the first direction.

6 . The memory device of claim 1 , wherein the first terminal is in contact with the first semiconductor layer, and the peripheral circuit is bonded with the second terminal.

7 . The memory device of claim 6 , further comprising:
a contact structure penetrating the first semiconductor layer in contact with a pad-out structure and the peripheral circuit and extending in the first direction between the first side of the first semiconductor layer and the peripheral circuit.

8 . The memory device of claim 7 , wherein the pad-out structure is disposed on a second side of the first semiconductor layer.

9 . The memory device of claim 1 , wherein the first terminal, the second terminal, the word line, and the plate line are controlled to collectively perform a memory write operation, a memory read operation, and a memory erase operation.

10 . A system, comprising:
a memory device, comprising:
an array of memory cells disposed on a first side of a first semiconductor layer, wherein each of the memory cells comprises:
a semiconductor body extending in a first direction, wherein a first terminal and a second terminal are formed at both ends of the semiconductor body;
a word line extending in a second direction perpendicular to the first direction;
a plate line extending in the second direction; and
a dielectric layer disposed between the semiconductor body and the word line and the plate line; and

a peripheral circuit bonded to the array of memory cells; and
a memory controller coupled to the memory device and configured to control operations of the array of memory cells through the peripheral circuit.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wang Di
• Liu Lei
• Yang Yuancheng
• Zhou Wenxi
• Zhang Kun
• Yang Tao
• Zhao Dongxue
• Xia Zhiliang
• Huo Zongliang

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title