Forwarded supply voltage for dynamic voltage and frequency scaling with stacked chip packaging architecture

Patent metadata

Field	Value
Publication number	US-12519084-B2
Application number	US-202217588392-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Jan 31, 2022
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die in a first layer; an interposer in a second layer not coplanar with the first layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the interposer coupling the first IC die and a second IC die. The first IC die is configured to transmit at a first supply voltage through the first conductive pathway to a second IC die, the second IC die is configured to transmit to the first IC die through the second conductive pathway at a second supply voltage simultaneously with the first die transmitting at the first supply voltage, and the first supply voltage is different from the second supply voltage.

First claim

The invention claimed is:

1 . A microelectronic assembly, comprising:
a first integrated circuit (IC) die in a first layer; an interposer in a second layer not coplanar with the first layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the interposer coupling the first IC die and a second IC die, wherein:
the first IC die comprises first circuitry to transmit a first data signal at a first supply voltage through the first conductive pathway to the second IC die,
the second IC die comprises second circuitry to transmit a second data signal to the first IC die through the second conductive pathway at a second supply voltage simultaneously with transmission of the first data signal at the first supply voltage by the first IC die, and the first supply voltage is different from the second supply voltage.

2 . The microelectronic assembly of claim 1 , wherein:
the first circuitry is to transmit at the first supply voltage through the interposer to a third IC die, the third IC die comprises third circuitry to transmit at a third supply voltage through the interposer to the first IC die simultaneously with the first IC die transmitting at the first supply voltage, and the third supply voltage is different from the first supply voltage.

3 . The microelectronic assembly of claim 1 , wherein:
a first transmission circuit in the first IC die is configured to transmit the first data signal to a first receiver circuit in the second IC die at the first supply voltage, and a second receiver circuit in the first IC die is configured to receive the second data signal from a second transmission circuit in the second IC die at the second supply voltage.

4 . The microelectronic assembly of claim 3 , wherein:
the first transmission circuit is configured to transmit at a first frequency, the second transmission circuit is configured to transmit at a second frequency, and the first frequency is different from the second frequency.

5 . The microelectronic assembly of claim 3 , wherein a first range of maximum operating frequencies and corresponding supply voltages of the first transmission circuit is different from a second range of maximum operating frequencies and the corresponding supply voltages of the second transmission circuit.

6 . The microelectronic assembly of claim 1 , wherein:
the interposer comprises a third IC die, and each of the first conductive pathway and the second conductive pathway is through a metallization stack in the first IC die, at least one of the interconnects, and another metallization stack in the third IC die.

7 . The microelectronic assembly of claim 6 , wherein the interposer further comprises a dielectric material surrounding the third IC die with through-dielectric vias (TDVs) in the dielectric material.

8 . The microelectronic assembly of claim 1 , further comprising the second IC die, wherein:
the second IC die is in the first layer, and each of the first conductive pathway and the second conductive pathway is through a first metallization stack in the first IC die, at least one of the interconnects between the first IC die and the interposer, a second metallization stack in the second IC die, at least one of the interconnects between the second IC die and the interposer, and a third metallization stack in the interposer.

9 . The microelectronic assembly of claim 8 , further comprising a package substrate coupled to the second layer.

10 . A microelectronic assembly, comprising:
a first integrated circuit (IC) die in a first layer; an interposer in a second layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the interposer coupling the first IC die and a second IC die, wherein:
the first IC die comprises first circuitry to transmit a first clock signal at a first supply voltage through the first conductive pathway to the second IC die,
the second IC die comprises second circuitry to transmit a second clock signal to the first IC die through the second conductive pathway at a second supply voltage simultaneously with transmission of the first clock signal at the first supply voltage by the first IC die, and
the first supply voltage is different from the second supply voltage.

11 . The microelectronic assembly of claim 10 , wherein:
the first circuitry is to transmit at the first supply voltage through the interposer to a third IC die, the third IC die comprises third circuitry to transmit at a third supply voltage through the interposer to the first IC die simultaneously with the first IC die transmitting at the first supply voltage, and the third supply voltage is different from the first supply voltage.

12 . The microelectronic assembly of claim 10 , wherein:
a first transmission circuit in the first IC die is configured to transmit the first clock signal to a first receiver circuit in the second IC die at the first supply voltage, and a second receiver circuit in the first IC die is configured to receive the second clock signal from a second transmission circuit in the second IC die at the second supply voltage.

13 . The microelectronic assembly of claim 12 , wherein:
the first transmission circuit is configured to transmit at a first frequency, the second transmission circuit is configured to transmit at a second frequency, and the first frequency is different from the second frequency.

14 . The microelectronic assembly of claim 12 , wherein a first range of maximum operating frequencies and corresponding supply voltages of the first transmission circuit is different from a second range of maximum operating frequencies and the corresponding supply voltages of the second transmission circuit.

15 . The microelectronic assembly of claim 10 , wherein:
the interposer comprises a third IC die, and each of the first conductive pathway and the second conductive pathway is through a metallization stack in the first IC die, at least one of the interconnects, and another metallization stack in the third IC die.

16 . The microelectronic assembly of claim 15 , wherein the interposer further comprises a dielectric material surrounding the third IC die with through-dielectric vias (TDVs) in the dielectric material.

17 . A microelectronic assembly, comprising:
a first integrated circuit (IC) die in a first layer; an IC structure in a second layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the IC structure coupling the first IC die and a second IC die, wherein:
the first IC die comprises first circuitry to transmit a first data signal at a first supply voltage and a first frequency through the first conductive pathway to the second IC die,
the second IC die comprises second circuitry to transmit a second data signal to the first IC die through the second conductive pathway at a second supply voltage and a second frequency simultaneously with transmission of the first data signal by the first IC die, and
the first supply voltage is different from the second supply voltage.

18 . The microelectronic assembly of claim 17 , wherein:
the first circuitry is to transmit at the first supply volta

Assignees

• Intel Corp

Inventors

• Pasdast Gerald S
• Wang Peipei
• Elsherbini Adel A

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title