Multiple die package using an embedded bridge connecting dies

Patent metadata

Field	Value
Publication number	US-12519062-B2
Application number	US-202318221184-A
Country	US
Kind code	B2
Filing date	Jul 12, 2023
Priority date	Mar 22, 2017
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

First claim

The invention claimed is:

1 . A microelectronic package comprising:
a package substrate; a silicon bridge embedded in the substrate; a first interconnect having a first plurality of contacts at a first location of the silicon bridge, the first interconnect for coupling to a first die; a second interconnect having a second plurality of contacts at a second location of the silicon bridge, the second interconnect for coupling to a second die; a third interconnect having a third plurality of contacts at a third location of the silicon bridge, the third interconnect for coupling to a third die, wherein the second interconnect is laterally between the first interconnect and the third interconnect, and wherein the first plurality of contacts, the second plurality of contacts and the third plurality of contacts are in a same plane; and an electrically conductive line in the silicon bridge laterally connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

2 . The package of claim 1 , wherein:
the substrate contains a well having a buffer material therein; and the silicon bridge is embedded in the well adjacent to the buffer material.

3 . The package of claim 2 , further comprising a dielectric over the silicon bridge and a plurality of copper pillars each over one of the first plurality of contacts.

4 . The package of claim 3 , wherein the copper pillars each comprise an interlocking feature to connect to a bump of a die over the first interconnect.

5 . The package of claim 1 , wherein a width of the electrically conductive line is no greater than approximately 0.2 microns.

6 . The package of claim 1 , wherein the package substrate is formed of an organic material and metal layers.

7 . The package of claim 1 , wherein the silicon bridge is embedded within the top five metal layers and wherein the first two metal layers are covered with a dielectric.

8 . The package of claim 1 , wherein the bridge is narrower than the second die attached to the second interconnect and shorter than the first die attached to the first interconnect so that the area of the bridge under the first die and the second die is less than the area of the first die and the second die on the package substrate.

9 . A method of manufacturing a microelectronic package comprising:
forming a well in organic layers of a package substrate; placing a silicon bridge into the well, the bridge having a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, and a third interconnect having a third plurality of contacts at a third location of the silicon bridge, wherein the second interconnect is laterally between the first interconnect and the third interconnect, wherein the silicon bridge further comprises an electrically conductive line laterally connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other; covering the silicon bridge with a dielectric; forming vias through the dielectric to the first, second, and third interconnects; attaching a first die over the first interconnect to connect to the first interconnect through the respective via; attaching a second die over the second interconnect to connect to the second interconnect through the respective via; and attaching a third die over the third interconnect to connect to the third interconnect through the respective via.

10 . The method of claim 9 , further comprising applying an adhesive in the well before placing the silicon bridge.

11 . The method of claim 9 , wherein attaching the first die comprises attaching the first die over the dielectric covering the silicon bridge.

12 . The method of claim 11 , wherein attaching the second die comprises attaching the second die over the dielectric covering the silicon bridge.

13 . The method of claim 12 , wherein attaching the third die comprises attaching the third die over the dielectric covering the silicon bridge.

14 . The method of claim 9 , wherein attaching the second die comprises attaching the second die over the dielectric covering the silicon bridge.

15 . A computing system comprising:
a circuit board; a mass memory attached to the circuit board; and a multi-chip package attached to the circuit board and coupled to the mass memory through the circuit board, the package including a package substrate, a silicon bridge embedded in the substrate, a first interconnect coupled to a first die and having a first plurality of contacts at a first location of the silicon bridge, a second interconnect coupled to a second die and having a second plurality of contacts at a second location of the silicon bridge, and a third interconnect coupled to a third die and having a third plurality of contacts at a third location of the silicon bridge, wherein the second interconnect is laterally between the first interconnect and the third interconnect, and the multi-chip package comprising an electrically conductive line in the silicon bridge laterally connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

16 . The computing system of claim 15 , wherein the second die acts as a master to the first die and the second die that are coupled to the host through the silicon bridge.

17 . The computing system of claim 15 , further comprising a second electrically conductive line in the silicon bridge connecting a second contact of the first interconnect to a second contact of the second interconnect and a second contact of the third interconnect to form a ring connection topology.

Assignees

• Intel Corp

Inventors

• Mekonnen Yidnekachew S
• Aygun Kemal
• Mahajan Ravindranath V
• Baldwin Christopher S
• Swaminathan Rajasekaran

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/695

  Organic materials · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title