Semiconductor device with first and second conductors and plated layer and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12519045-B2
Application number	US-202117928724-A
Country	US
Kind code	B2
Filing date	Feb 26, 2021
Priority date	Jun 8, 2020
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A semiconductor device includes: a semiconductor element; and a first conductor and a second conductor respectively joined to a first surface and a second surface of the semiconductor element via Sn-based solder, in which a Ni-based plated layer is formed on surfaces of the first conductor and the second conductor that oppose the Sn-based solder and on the first surface and the second surface of the semiconductor element, and an interface reaction inhibition layer made of (Cu, Ni)6Sn5 and having a layer thickness of 1.2 to 4.0 μm is formed at an interface between the Ni-based plated layer and the Sn-based solder.

First claim

The invention claimed is:

1 . A semiconductor device, comprising: a semiconductor element; and a first conductor and a second conductor respectively joined to a first surface and a second surface of the semiconductor element via Sn-based solder,
wherein a Ni-based plated layer is formed on surfaces of the first conductor and the second conductor that oppose the Sn-based solder and on the first surface and the second surface of the semiconductor element, and an interface reaction inhibition layer made of (Cu, Ni) 6 Sn 5 and having a layer thickness of 1.2 to 4.0 μm is formed at an interface between the Ni-based plated layer and the Sn-based solder, and wherein the first conductor is an emitter-side conductor, the second conductor is a collector-side conductor, and in a solder joint formed of the Sn-based solder and the interface reaction inhibition layer, an emitter-side solder joint is thicker than a collector-side solder joint.

2 . The semiconductor device according to claim 1 , wherein
the interface reaction inhibition layer has a layer thickness of 1.4 to 3.2 μm.

3 . The semiconductor device according to claim 1 , wherein
the Sn-based solder is blended with a Cu member.

4 . The semiconductor device according to claim 1 , wherein
the emitter-side solder joint has a thickness of 120 to 200 μm, and the collector-side solder joint has a thickness of 70 to 100 μm.

5 . The semiconductor device according to claim 1 , wherein
the emitter-side Sn-based solder has a Cu content of equal to or greater than 2 mass %, and does not contain Ag.

6 . The semiconductor device according to claim 1 , wherein
the collector-side Sn-based solder has a Cu content of equal to or greater than 2 mass % and contains 2 to 4 mass % of Ag.

7 . A method for manufacturing a semiconductor device, the method, comprising:
forming a Ni plated layer on a collector-side lead frame; supplying, onto the Ni plated layer, Sn—Ag—Cu-based solder blended with a Cu member and having a Cu content of equal to or greater than 1.5 mass %, and joining a semiconductor element; and supplying, onto the semiconductor element, Sn—Cu-based solder having a Cu content of equal to or greater than 1.5 mass %, and joining an emitter-side lead frame on which Cu plating is applied onto a Ni plated layer.

8 . A method for manufacturing a semiconductor device, the method, comprising:
forming a Ni plated layer on a collector-side lead frame; forming Cu plating on the Ni plated layer; supplying Sn—Ag—Cu-based solder having a Cu content of equal to or greater than 1.5 mass % onto the Cu plating, and joining a semiconductor element; and supplying, onto the semiconductor element, Sn—Cu-based solder having a Cu content of equal to or greater than 1.5 mass %, and joining an emitter-side lead frame on which Cu plating is applied onto a Ni plated layer.

Assignees

• Hitachi Astemo Ltd

Inventors

• Ikeda Osamu
• Takagi Yusuke
• Kaneko Yujiro
• Funato Shota

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/347

  Dispositions of multiple die-attach connectors · CPC title

• H10W72/07354

  changes in dispositions · CPC title