Memory interface between physical and virtual address spaces

Patent metadata

Field	Value
Publication number	US-10936509-B2
Application number	US-201815922194-A
Country	US
Kind code	B2
Filing date	Mar 15, 2018
Priority date	Feb 28, 2018
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising: a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and a coherency manager comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space; wherein the memory interface is configured to: receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space; translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus; receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and translate the snoop request, at the coherency manager, to a translated snoop request addressed in the virtual address space for processing in connection with the cache memory.

First claim

What is claimed is:

1. A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising:
a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and
a coherency manager comprising a reverse translation module having a reverse translation data structure configured to maintain a mapping from the physical address space to the virtual address space, and the coherency manager being configured to maintain, at the reverse translation data structure, entries only for coherent cache lines held in the cache memory;

wherein the memory interface is configured to:
receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space;
translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus;
receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and
translate the snoop request, at the coherency manager, to a translated snoop request addressed in the virtual address space for processing in connection with the cache memory.

2. The memory interface according to claim 1 , in which the reverse translation module comprises logic for calculating the virtual address in dependence on the physical address, based on a known relationship between the physical address space and the virtual address space.

3. The memory interface according to claim 1 , in which the reverse translation data structure comprises a directory linking a physical address in the physical address space to a corresponding virtual address in the virtual address space.

4. The memory interface according to claim 1 , in which the reverse translation data structure comprises one or more field associated with each physical to virtual address mapping entry, the one or more field being for storing data relating to the mapping.

5. The memory interface according to claim 4 , in which the coherency manager is configured to process the snoop request in dependence on the data relating to the mapping stored in the one or more field.

6. The memory interface according to claim 5 , in which the one or more field comprises a state field for indicating an overall state of the entry, and where the state field indicates that the entry is in an invalid state, the coherency manager is configured to determine that the snoop request results in a cache miss and to cause a corresponding response to the snoop request to be sent on the bus.

7. The memory interface according to claim 1 , in which, where the reverse translation data structure does not comprise a mapping for a particular physical address, the coherency manager is configured to determine that the snoop request results in a cache miss and to cause a corresponding response to the snoop request to be sent on the bus.

8. The memory interface according to claim 1 , comprising a cache line status data structure configured to store status information relating to cache lines associated with each virtual address mapped at the reverse translation module.

9. The memory interface according to claim 8 , in which the coherency manager is configured to process the snoop request in dependence on the status information relating to the cache line stored in the cache line status data structure.

10. The memory interface according to claim 9 , in which, where the status information relating to the cache line indicates that the cache line is at least one of:
in an invalid state,
undergoing spilling, and
undergoing a writeback or eviction process,

the coherency manager is configured to determine that the snoop request results in a cache miss and to cause a corresponding response to the snoop request to be sent on the bus.

11. The memory interface according to claim 1 , comprising a buffer configured to store one or more intermediate response generated in response to the received snoop request, the memory interface being configured to respond to the snoop request in dependence on the stored one or more intermediate response.

12. The memory interface according to claim 1 , in which the coherency manager is configured to determine a fill level of at least one of the reverse translation data structure and the cache, and to evict cache line data from the cache memory in dependence on determining that the fill level exceeds a fill level threshold.

13. The memory interface according to claim 12 , in which the memory interface is configured to allocate new data to a cache line undergoing writeback and/or eviction before the writeback and/or eviction process completes, to store data relating to the allocation, and to respond to the received snoop request in dependence on the stored data relating to the allocation.

14. The memory interface according to claim 1 , in which the memory interface is configured to:
cause at least one of the snoop request and the translated snoop request relating to a particular cache line to be stored in a queue, and
prior to processing the translated snoop request, permit a subsequent snoop request relating to the particular cache line to be processed.

15. The memory interface according to claim 1 , in which the coherency manager is configured to store a request counter indicating the number of outstanding requests on cache lines within a memory page, to increment the request counter in response to a snoop request, and to decrement the request counter in response to a snoop request response, in which the coherency manager is configured to restrict eviction of a cache line in the memory page where the request counter is non-zero.

16. The memory interface according to claim 1 , in which the cache memory comprises a plurality of cache banks and the memory interface is configured to determine the cache bank to which the translated snoop request is addressed in dependence on the reverse translation module, the memory interface being configured to process the translated snoop request at the determined cache bank.

17. A method for interfacing, at a memory interface, between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising a memory management unit configured to maintain a mapping from the virtual address space to the physical address space so as to translate a received memory read request from the cache memory addressed in the virtual address space to a translated memory read request addressed in the physical address space for transmission on the memory bus, and a coherency manager comprising a reverse translation module having a reverse translation data structure configured to maintain a mapping from the physical address space to the virtual address space, and the coherency manager being configured to maintain, at the reverse translation data structure, entries only for coherent cache lines held in the cache memory; the method comprising:
receiving a snoop request from the memory bus, the snoop request being addressed in the physical address space; and
translating the snoop request, at the coherency manager, to a translated snoop request addressed in the virtual address space for processing in connection with the cache memory.

18. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that,

Assignees

• Imagination Tech Ltd

Inventors

• Robinson Martin John
• Landers Mark

Classifications

• G06F12/0877

  Cache access modes · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F12/1063 Primary

  the data cache being concurrently virtually addressed · CPC title