Neural network based prediction of semiconductor device response

Patent metadata

Field	Value
Publication number	US-12512370-B2
Application number	US-202218052654-A
Country	US
Kind code	B2
Filing date	Nov 4, 2022
Priority date	Nov 19, 2021
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

A computer-implemented method for evaluating a semiconductor wafer. In accordance with the present invention, using a properly designed neural network, the computer can take image data regarding the wafer at issue, plus image and electrical data regarding a prior wafer and devices fabricated on the prior wafer, to find relations to and between structural features, both known and previously unidentified, that can degrade the performance of devices fabricated on the wafer and/or can reduce the device yield of the wafer.

First claim

What is claimed is:

1 . A neural network-based method for evaluating a semiconductor wafer response based on fabricating of electronic devices thereon, including the steps of:
performing an initial evaluation of the semiconductor wafer based on a position of the electronic device thereon; inputting data from the initial evaluation into a neural network that performs an iterative evaluation of the wafer based on the initial evaluation and prior evaluations performed by the neural network based on trained data; and outputting data regarding at least one performance metric of the electronic device that could be fabricated on the wafer; wherein the output data includes data indicating performance of the electronic device fabricated at a plurality of locations on the wafer, and probability that a device fabricated at a predetermined location on the wafer will exceed a predetermined functional threshold.

2 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the data input into the neural network includes data of an evaluation of a prior wafer into the neural network.

3 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the data input into the neural network includes optical microscopy images, optical profilometry images, Nomarski images, fluorescent images, or ultraviolet images taken of the wafer being evaluated or of a prior wafer.

4 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the data input into the neural network includes photoluminescence, electroluminescence, cathodoluminescence, and/or Auger spectroscopy images of the wafer being evaluated or of a prior wafer.

5 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the data input into the neural network includes scanning electron micrographs, atomic force microscopy images, x-ray diffraction (XRD) mapping image, or Raman mapping images of the wafer being evaluated or of a prior wafer.

6 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the neural network is a multi-layer convolutional neural network (CNN).

7 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the neural network is a gated recurrent unit (GRU) network, long short term memory (LSTM) network, or similar recurrent neural network.

8 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the performance metric is a current-voltage (IV) response or a capacitance-voltage (CV) response of the electronic device fabricated on at least one area of the wafer.

9 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the performance metric is an ON-resistance performance, stable operating voltage, or maximum operating frequency of the electronic device.

10 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the performance metric is a turn-on time or rate or turn-off time or rate in response to an input change as a function of time.

11 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the performance metric is an output power or gain as a function of frequence.

12 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the output data includes data indicative of an optimum geometric configuration or a maximum or minimum size of a device to be fabricated at a predetermined location on the wafer.

13 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the output data includes data indicative of a pass/fail Boolean metric of a device to be fabricated at a predetermined location on the wafer.

14 . The method for evaluating a semiconductor wafer according to claim 1 , wherein the output data includes data at least one performance metric of an opto-electronic device that could be fabricated on the wafer.

15 . The method for evaluating a semiconductor wafer according to claim 1 , wherein outputting data regarding at least one performance metric for an integrated circuit that could be fabricated on the wafer.

Assignees

• Us Gov Sec Navy

Inventors

• Mastro Michael A
• Gallagher James
• Anderson Travis J

Classifications

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G06T2207/30148

  Semiconductor; IC; Wafer · CPC title

• G06T2207/20084

  Artificial neural networks [ANN] · CPC title

• G06T7/001

  using an image reference approach · CPC title

• G06N3/0442

  characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title