Dynamic yield prediction

Patent metadata

Field	Value
Publication number	US-9470743-B2
Application number	US-201414196219-A
Country	US
Kind code	B2
Filing date	Mar 4, 2014
Priority date	Mar 4, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

Dynamic yield prediction. In accordance with a first method embodiment of the present invention, a computer-implemented method includes collecting sample test information from a plurality of test-only structures prior to completion of the first wafer, gathering finished test data from all die of the first wafer, after completion of the first wafer, constructing a yield prediction model based on the sample test information and on the finished test data, and predicting, using the model, a percentage of die of the first wafer that will meet a particular specification. The method may further include a feedback loop to dynamically update the model.

First claim

What is claimed is:

1. A computer-implemented method comprising:
collecting sample test information from a plurality of test-only structures of a first wafer, prior to completion of said first wafer;
gathering finished test data from all die of said first wafer, after completion of said first wafer;
constructing a yield prediction model based on said sample test information and on said finished test data; and
predicting, using said model, a percentage of die of said first wafer that will meet a particular specification.

2. The computer-implemented method of claim 1 further comprising:
collecting second sample test information from a plurality of test-only structures of a second wafer, prior to completion of said second wafer; and
predicting, using said model, a percentage of die of said second wafer that will meet a particular specification.

3. The computer-implemented method of claim 2 further comprising:
gathering second finished test data from all die of said second wafer, after completion of said second wafer; and
constructing a refined yield prediction model based on said second sample test information and on said second finished test data.

4. The computer-implemented method of claim 3 wherein said refined yield prediction model is adjusted to reflect current process maturity.

5. The computer-implemented method of claim 1 wherein said plurality of test-only structures is limited to nine or fewer of said test-only structures.

6. The computer-implemented method of claim 1 wherein said collecting is performed after production of a second metallization layer and prior to production of any subsequent metallization.

7. The computer-implemented method of claim 1 wherein said test-only structures comprise an inter-metallic wafer acceptance test transistor formed in a scribe line of said first wafer.

8. An article of manufacture including a computer readable medium having instructions stored thereon that, responsive to execution by an electronic system, cause said electronic system to perform operations comprising:
collecting sample test information from a plurality of test-only structures of a first wafer, prior to completion of said first wafer;
gathering finished test data from all die of said first wafer, after completion of said first wafer;
constructing a yield prediction model based on said sample test information and on said finished test data; and
predicting, using said model, a percentage of die of said first wafer that will meet a particular specification.

9. The article of manufacture of claim 8 further comprising:
collecting second sample test information from a plurality of test-only structures of a second wafer, prior to completion of said second wafer; and
predicting, using said model, a percentage of die of said second wafer that will meet a particular specification.

10. The article of manufacture of claim 9 further comprising:
gathering second finished test data from all die of said second wafer, after completion of said second wafer; and
constructing a refined yield prediction model based on said second sample test information and on said second finished test data.

11. The article of manufacture of claim 10 wherein said refined yield prediction model is adjusted for changes in process variation.

12. The article of manufacture of claim 8 wherein said plurality of test-only structures is limited to nine or fewer of said test-only structures.

13. The article of manufacture of claim 8 wherein said collecting is performed after production of a second metallization layer and prior to production of any subsequent metallization.

14. The article of manufacture of claim 8 wherein said test-only structures comprise a ring oscillator formed in a scribe line of said first wafer.

15. An apparatus comprising:
means for collecting sample test information from a plurality of test-only structures of a first wafer, prior to completion of said first wafer;
means for gathering finished test data from all die of said first wafer, after completion of said first wafer;
means for constructing a yield prediction model based on said sample test information and on said finished test data; and
means for predicting, using said model, a percentage of die of said first wafer that will meet a particular specification.

16. The apparatus of claim 15 further comprising:
means for collecting second sample test information from a plurality of test-only structures of a second wafer, prior to completion of said second wafer; and
means for predicting, using said model, a percentage of die of said second wafer that will meet a particular specification.

17. The apparatus of claim 16 further comprising:
means for gathering second finished test data from all die of said second wafer, after completion of said second wafer; and
means for constructing a refined yield prediction model based on said second sample test information and on said second finished test data.

18. The apparatus of claim 17 wherein said refined yield prediction model is adjusted to reflect current process maturity.

19. The apparatus of claim 15 wherein said plurality of test-only structures is limited to nine or fewer of said test-only structures.

20. The apparatus of claim 15 wherein said means for collecting further comprises means for collecting said sample test information from a plurality of test-only structures after production of a second metallization layer and prior to production of any subsequent metallization.

Assignees

• Nvidia Corp

Inventors

• Callegari Nicholas
• Cory Bruce
• Greco Joe

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G06F30/333

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title