Method of determining and preprogramming over-erases groups of memory cells

Patent metadata

Field	Value
Publication number	US-12512170-B2
Application number	US-202318385185-A
Country	US
Kind code	B2
Filing date	Oct 30, 2023
Priority date	Feb 24, 2023
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

A method of controlling a nonvolatile memory device, includes: determining, based on a write address, whether selected memory cells of the nonvolatile memory device corresponding to the write address are included in an over-erased group; based on the selected memory cells being included in the over-erased group, performing a preprogram operation to increase threshold voltages of an over-erased state of the selected memory cells; and after completion of the preprogram operation, performing a data program operation to store write data in the selected memory cells.

First claim

What is claimed is:

1 . A method of controlling a nonvolatile memory device, the method comprising:
determining, based on a write address, whether selected memory cells of the nonvolatile memory device corresponding to the write address are included in an over-erased group; based on the selected memory cells being included in the over-erased group, performing a preprogram operation to increase threshold voltages of an over-erased state of the selected memory cells; and after completion of the preprogram operation, performing a data program operation to store write data in the selected memory cells, wherein the preprogram operation comprises decreasing a preprogram voltage applied to a selected wordline corresponding to the write address during the preprogram operation, as a distance between a selected string selection line corresponding to the selected memory cells and a wordline cut area decreases.

2 . The method of claim 1 , wherein the preprogram voltage applied to a selected wordline corresponding to the write address during the preprogram operation is lower than a data program voltage applied to the selected wordline during the data program operation.

3 . The method of claim 1 , wherein a preprogram pass voltage applied to non-selected wordlines, other than a selected wordline corresponding to the write address, during the preprogram operation is lower than a data program pass voltage applied to the non-selected wordlines during the data program operation.

4 . The method of claim 1 , wherein a pre-verification read voltage applied to a selected wordline corresponding to the write address during the preprogram operation is lower than a data verification read voltage applied to the selected wordline during the data program operation.

5 . The method of claim 1 , wherein the write address corresponds to a physical address of the nonvolatile memory device, and
wherein the determining whether the selected memory cells are included in the over-erased group comprises determining whether the selected memory cells are included in the over-erased group based on a physical position of the selected memory cells.

6 . The method of claim 1 , wherein the determining whether the selected memory cells are included in the over-erased group comprises:
determining on a second distance between channel holes including the selected memory cells and the wordline cut area; and determining, based on the second distance, whether the selected memory cells are included in the over-erased group.

7 . The method of claim 1 , wherein the determining whether the selected memory cells are included in the over-erased group comprises:
based on a selected string selection line that corresponds to the selected memory cells corresponding to an outermost string selection line that is closest to a the wordline cut area, determining that the selected memory cells are included in the over-erased group; and based on the selected string selection line not corresponding to the outermost string selection line, determining that the selected memory cells are not included in the over-erased group.

8 . The method of claim 1 , wherein the determining whether the selected memory cells are included in the over-erased group comprises:
based on channel holes including the selected memory cells corresponding to outermost channel holes closest to a the wordline cut area, determining that the selected memory cells are included in the over-erased group; and based on the channel holes including the selected memory cells not corresponding to the outermost channel holes, determining that the selected memory cells are not included in the over-erased group.

9 . The method of claim 1 , wherein the determining whether the selected memory cells are included in the over-erased group comprises:
determining whether the selected memory cells are included in the over-erased group, based on an interval between a selected wordline corresponding to the write address and a neighboring wordline adjacent to the selected wordline.

10 . The method of claim 1 , wherein the determining whether the selected memory cells are included in the over-erased group comprises:
based on an interval between a selected wordline corresponding to the write address and a neighboring wordline adjacent to the selected wordline being smaller than a reference interval, determining that the selected memory cells are included in the over-erased group; and based on the interval between the selected wordline and the neighboring wordline being greater than the reference interval, determining that the selected memory cells are not included in the over-erased group.

11 . The method of claim 1 , wherein performing the preprogram operation comprises:
performing a pre-verification operation by applying a pre-verification read voltage to the selected wordline corresponding to the write address to determine over-erased memory cells having threshold voltages lower than the pre-verification read voltage among the selected memory cells; and after the performing the pre-verification operation, performing a preprogram execution operation by applying the preprogram voltage to the selected wordline to increase the threshold voltages of the over-erased memory cells.

12 . The method of claim 11 , wherein the pre-verification read voltage is lower than a data verification read voltage corresponding to a lowest program state of the data program operation, and
wherein the preprogram voltage is lower than a data program voltage corresponding to the lowest program state of the data program operation.

13 . The method of claim 11 , wherein the selected memory cells having the threshold voltages lower than the pre-verification read voltage are determined as the over-erased memory cells regardless of the write data.

14 . The method of claim 11 , further comprising repeatedly performing the pre-verification operation and the preprogram execution operation while increasing the preprogram voltage in a step-by-step manner.

15 . The method of claim 1 , wherein the preprogram operation is performed during the nonvolatile memory device receives the write data from a host device.

16 . The method of claim 1 , wherein, when the selected memory cells are not included in the over-erased group, the preprogram operation is omitted and only the data program operation is performed.

17 . A method of controlling a nonvolatile memory device, the method comprising:
determining, based on a write address, whether selected memory cells of the nonvolatile memory device corresponding to the write address are included in an over-erased group; based on the selected memory cells being included in the over-erased group, performing a preprogram operation to increase threshold voltages of an over-erased state of the selected memory cells; and after completion of the preprogram operation, performing a data program operation to store write data in the selected memory cells, wherein a time point of starting the data program operation is uniform regardless of whether the preprogram operation is performed or omitted.

18 . A nonvolatile memory device comprising:
a memory cell array comprising a plurality of memory cells; and a control circuit configured to: based on selected memory cells corresponding to a write address being included in an over-erased group, perform a preprogram operation to increase threshold voltages of an over-erased state of the selected memory cells, and after performing the preprogram operation, performing a data program operation to s

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yohan
• Yu Jaeduk
• Park Sangsoo
• Choi Yonghyuk

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/345 Primary

  Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification · CPC title