Memory device and operating method thereof

Patent metadata

Field	Value
Publication number	US-10490284-B2
Application number	US-201815926011-A
Country	US
Kind code	B2
Filing date	Mar 20, 2018
Priority date	Aug 21, 2017
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

First claim

What is claimed is:

1. A memory device, comprising:
a memory cell array including a plurality of memory cells;
a peripheral circuit performing a program operation on selected memory cells among the plurality of memory cells; and
a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

2. The memory device of claim 1 , wherein the control logic includes a program operation control unit controlling the peripheral circuit to apply an additional program voltage to a selected word line coupled to the selected memory cells so that the threshold voltage of the memory cells corresponding to the deep erased state is increased to the threshold voltage corresponding to the erase state during the additional program operation.

3. The memory device of claim 2 , wherein the program operation control unit controls the peripheral circuit to apply the additional program voltage to the selected word line several times during the additional program operation.

4. The memory device of claim 2 , wherein the peripheral circuit includes a voltage generator generating the additional program voltage.

5. The memory device of claim 1 , wherein the control logic controls the peripheral circuit to determine whether the memory cells corresponding to the deep erased state exist, among the selected memory cells, after the program operation is completed, and performs the additional program operation thereon when the memory cells corresponding to the deep erased state exist.

6. A memory device, comprising:
a memory cell array including a plurality of memory cells divided into a plurality of pages;
a peripheral circuit performing a program operation on a selected page, among the plurality of pages; and
a program operation control unit controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells have a threshold voltage having a lower voltage level than a threshold voltage corresponding to an erase state, the memory cells included in at least one of the plurality of pages, after the program operation is completed.

7. The memory device of claim 6 , wherein the program operation control unit controls the peripheral circuit to perform an additional program operation on the memory cells corresponding to the deep erased state included in the selected page when the program operation of the selected page is completed.

8. The memory device of claim 7 , wherein the program operation control unit determines whether the memory cells corresponding to the deep erased state are included in the selected page, and performs the additional program operation thereon according to a result of determination.

9. The memory device of claim 6 , wherein the program operation control unit controls the peripheral circuit to simultaneously or sequentially perform additional program operations on the selected page and a previous page programmed prior to the selected page when the program operation of the selected page is completed.

10. The memory device of claim 9 , wherein the program operation control unit determines whether the memory cells corresponding to the deep erased state are included in the selected page and the previous page, and performs the additional program operations according to a result of determination.

11. The memory device of claim 6 , wherein the program operation control unit controls the peripheral circuit to simultaneously or sequentially perform additional program operations on the selected page, the previous page programmed prior to the selected page, and a next page to be programmed subsequent to the selected page when the program operation of the selected page is completed.

12. The memory device of claim 11 , wherein the program operation control unit determines whether the memory cells corresponding to the deep erased state are included in the selected page, the previous page and the next page, and performs the additional program operations thereon according to a result of determination.

13. The memory device of claim 6 , wherein the program operation control unit controls the peripheral circuit to apply an additional program voltage to a page on which the additional program operations are performed, among the plurality of pages, at least once during the additional program operation.

14. The memory device of claim 13 , wherein the additional program voltage is applied to increase the threshold voltage of the memory cells corresponding to the deep erased state to the erase state.

15. The memory device of claim 14 , wherein the peripheral circuit includes a voltage generator generating the additional program voltage.

16. A method of operating a memory device, the method comprising:
performing a program operation on memory cells included in a selected page, among a plurality of memory cells forming a plurality of pages; and
performing an additional program operation on memory cells corresponding to a deep erased state where the memory cells have a lower threshold voltage than an erase state, the memory cells included in at least one of the plurality of pages, after the program operation is completed.

17. The method of claim 16 , wherein the performing of the additional program operation comprises:
determining whether the memory cells corresponding to the deep erased state are included in the selected page and a previous page programmed prior to the selected page; and
supplying an additional program voltage to the selected page and the previous page to increase the threshold voltage of the memory cells corresponding to the deep erased state to the erase state when the memory cells corresponding to the deep erased state are included in the selected page and the previous page.

18. The method of claim 16 , wherein the performing of the additional program operation comprises:
determining whether the memory cells corresponding to the deep erased state are included in the selected page, the previous page programmed prior to the selected page, and a next page to be programmed subsequent to the selected page; and
supplying an additional program voltage to the selected page, the previous page and the next page to increase the threshold voltage of the memory cells corresponding to the deep erased state to the erase state when the memory cells corresponding to the deep erased state are included in the selected page, the previous page and the next page.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl
• Kwon Kyoung Cheol
• Lee Dong Hun
• Jeong Min Kyu
• Chung Sung Yong

Classifications

• G11C16/3409

  Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/3481

  Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming · CPC title