Post write erase conditioning

Patent metadata

Field	Value
Publication number	US-10818366-B2
Application number	US-202016744097-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	Mar 28, 2017
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

First claim

What is claimed is:

1. A data storage device, comprising:
a memory comprising blocks for programming data;
a controller coupled to the memory and configured to cause:
performing a post write erase conditioning operation comprising:
performing one or more read operations on one or more cells associated with one or more wordlines in a block of the memory;
identifying cells as deeply erased cells when a voltage of each of the cells is below a threshold voltage; and
reprogramming the deeply erased cells associated with fully programmed wordlines.

2. The data storage device of claim 1 , wherein the memory comprises a dielectric layer for charge trapping.

3. The data storage device of claim 1 , wherein the performing one or more read operations, the identifying and the reprogramming are performed as background operations.

4. The data storage device of claim 1 , wherein the reprogramming the deeply erased cells comprises reprogramming the deeply erased cells within a closed block having its wordlines fully programmed.

5. The data storage device of claim 1 , wherein the deeply erased cells have programmed data, wherein the reprogramming the deeply erased cells comprises reprogramming the deeply erased cells within an open block, and wherein not all wordlines of the open block are fully programmed.

6. The data storage device of claim 1 , wherein the performing one or more read operations and the identifying comprise iteratively performing a read operation on each wordline of the block for identifying each of the deeply erased cells in the block.

7. The data storage device of claim 1 , wherein the reprogramming narrows a distribution of an erase state for each of the deeply erased cells.

8. The data storage device of claim 7 , wherein the reprogramming comprises applying a voltage to the deeply erased cells that narrows and shifts the distribution of the erase state for each of the deeply erased cells.

9. The data storage device of claim 1 , wherein the memory is charge trap memory comprising a three-dimensional memory configuration, and wherein the controller is associated with operation of and storing to the charge trap memory.

10. The data storage device of claim 1 , wherein the reprogramming improves data retention by increasing a voltage level and narrowing a distribution of an erase state for the deeply erased cells.

11. A method, comprising:
performing a post write erase conditioning operation comprising:
performing one or more read operations on one or more cells associated with one or more wordlines in a block of a memory;
identifying cells having programmed data as deeply erased cells when a voltage of each of the cells is below a threshold voltage; and
reprogramming the deeply erased cells associated with fully programmed wordlines.

12. The method of claim 11 , wherein the performing one or more read operations, the identifying and the reprogramming are performed as background operations.

13. The method of claim 11 , wherein the reprogramming the deeply erased cells comprises reprogramming the deeply erased cells within a closed block, and wherein all wordlines of the closed block are fully programmed.

14. The method of claim 11 , wherein the reprogramming the deeply erased cells comprises reprogramming the deeply erased cells within an open block, and wherein not all wordlines of the open block are fully programmed.

15. The method of claim 11 , wherein the reprogramming comprises applying a voltage to the deeply erased cells that narrows and shifts a distribution of an erase state for each of the deeply erased cells.

16. The method of claim 11 , wherein the reprogramming improves data retention by increasing a voltage level and narrowing a distribution of an erase state for the deeply erased cells.

17. A storage device, comprising:
a memory comprising blocks; and
means for performing a post write erase conditioning operation comprising:
means for performing one or more read operations on one or more cells associated with one or more wordlines in a block of the memory;
means for identifying cells having programmed data as deeply erased cells when a voltage of each of the cells is below a threshold voltage; and
means for reprogramming the deeply erased cells associated with fully programmed wordlines.

18. The storage device of claim 17 , wherein the means for performing one or more read operations, the means for identifying and the means for reprogramming are configured to be performed as background operations.

19. The storage device of claim 17 , wherein the means for reprogramming the deeply erased cells comprises means for reprogramming the deeply erased cells within a closed block, and wherein all wordlines of the closed block are fully programmed.

20. The storage device of claim 17 , wherein the means for reprogramming the deeply erased cells comprises means for reprogramming the deeply erased cells within an open block, and wherein not all wordlines of the open block are fully programmed.

Assignees

• Western Digital Tech Inc

Inventors

• Dunga Mohan Vamsi
• Chen Changyuan
• Ray Biswajit

Classifications

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3409

  Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step · CPC title