Semiconductor wafer thinned by horizontal stealth lasing

US12506015B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12506015-B2
Application numberUS-202217841357-A
CountryUS
Kind codeB2
Filing dateJun 15, 2022
Priority dateJun 15, 2022
Publication dateDec 23, 2025
Grant dateDec 23, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method includes the step of thinning a semiconductor wafer by a horizontal stealth lasing process, and semiconductor wafers, dies and devices formed thereby. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by supporting an active surface of the wafer on a rotating chuck, and focusing a horizontally-oriented laser in multiple cycles at different radii within the rotating wafer. Upon completion of the multiple cycles, a portion of the wafer substrate may be removed, leaving the wafer thinned to its final thickness. Thereafter, a vertical stealth lasing process may be performed to cut individual semicondcutor dies from the thinned wafer.

First claim

Opening claim text (preview).

We claim: 1. A method of separating a semiconductor die from a wafer comprising a plurality of semiconductor dies, the wafer comprising a first major planar surface, a second major planar surface and an outer edge extending between the first and second major planar surfaces, wherein each die comprises a plurality of integrated circuits formed in the first major planar surface of the wafer, the method comprising: rotating the wafer; penetrating the outer edge of the wafer with a laser beam without removing portions of the outer edge; pulsing the laser at distinct points at a given radial distance from a center of the wafer; repeating said step of pulsing the laser at distinct points at multiple other radial distances from the center of the wafer; thinning the wafer by allowing cracks to propagate between the distinct points at multiple radii; and dicing the semiconductor die from the thinned wafer. 2. The method of claim 1 , wherein the wafer is supported on a chuck with the first major planar surface facing the chuck for said step of thinning the wafer. 3. The method of claim 2 , wherein said chuck rotates during said step of thinning the wafer. 4. The method of claim 2 , wherein a focal point of the laser is adjusted to different radial positions of the wafer as the wafer is rotating on the chuck to generate pinpoint holes at the different radial positions in a plane parallel to the first major surface. 5. The method of claim 1 , wherein the step of thinning the wafer by application of one or more laser beams through the outer edge of the wafer comprises the step of generating pinpoint holes from a pair of laser assemblies in a plane parallel to the first major planar surface of the wafer. 6. The method of claim 1 , wherein the step of dicing the semiconductor die from the thinned wafer comprises the step of generating pinpoint holes in a plane orthogonal to the first major planar surface of the wafer, cracks propagating between the pinpoint holes to dice the die from the wafer. 7. A method of separating a semiconductor die from a wafer comprising a plurality of semiconductor dies, the wafer comprising a first major planar surface, a second major planar surface and an outer edge extending between the first and second major planar surfaces, wherein each die comprises a plurality of integrated circuits formed in the first major planar surface of the wafer, the method comprising: rotating the wafer; pulsing a laser beam through the outer edge of the wafer as the wafer rotates to form focal points within an interior of the wafer, each focal point creating a localized pinpoint hole around a circle; changing one of a distance of the focal point from a laser beam generator, or a position of the laser beam generator from the wafer, to create multiple circles of localized pinpoint holes at different radii; thinning the wafer by allowing cracks to propagate between the localized pinpoint holes at different radii; and dicing the semiconductor die from the thinned wafer. 8. The method of claim 7 , wherein the wafer is supported on a chuck with the first major planar surface facing the chuck for said step of thinning the wafer. 9. The method of claim 8 , wherein said chuck rotates during said step of thinning the wafer. 10. The method of claim 7 , wherein the step of thinning the wafer by application of one or more laser beams through the outer edge of the wafer comprises the step of generating pinpoint holes from a pair of laser assemblies in a plane parallel to the first major planar surface of the wafer. 11. The method of claim 1 , wherein the step of dicing the semiconductor die from the thinned wafer comprises the step of generating pinpoint holes in a plane orthogonal to the first major planar surface of the wafer, cracks propagating between the pinpoint holes to dice the die from the wafer.

Assignees

Inventors

Classifications

  • characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating carrousel · CPC title

  • Mechanical treatments, e.g. by ultrasounds · CPC title

  • Cutting or separating of wafers, substrates or parts of devices · CPC title

  • H10P52/00Primary

    Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

  • Devices involving rotation of the workpiece · CPC title

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Frequently asked questions

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What does patent US12506015B2 cover?
A method includes the step of thinning a semiconductor wafer by a horizontal stealth lasing process, and semiconductor wafers, dies and devices formed thereby. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by supporting an active surface of the wafer on a rotating chuck, and focusing a horizontally-oriented laser in multiple cycles at differen…
Who is the assignee on this patent?
Western Digital Tech Inc, Sandisk Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H10P72/7618. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 23 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).