Power loss error detection using partial block handling

Patent metadata

Field	Value
Publication number	US-12505899-B2
Application number	US-202318492252-A
Country	US
Kind code	B2
Filing date	Oct 23, 2023
Priority date	Nov 22, 2022
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

In some implementations, a memory device may determine that a power loss has occurred. The memory device may determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device. The memory device may determine one of: a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio. The memory device may perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage.

First claim

What is claimed is:

1 . A memory device, comprising:
one or more components configured to:
determine that a power loss has occurred;
determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device;
determine one of:
a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or
a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio; and

perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio-dependent offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage associated with the power loss error detection procedure.

2 . The memory device of claim 1 , wherein the one or more components are further configured to:
determine the WLG associated with the LWP location and the at least one WLG-dependent offset associated with the WLG; and perform the power loss error detection procedure based on the at least one WLG-dependent offset.

3 . The memory device of claim 1 , wherein the one or more components are further configured to:
determine the PB fill ratio associated with the LWP location and the at least one PB-fill-ratio-dependent offset associated with the PB fill ratio; and perform the power loss error detection procedure based on the at least one PB-fill-ratio-dependent offset.

4 . The memory device of claim 1 , wherein the power loss error detection procedure is associated with a NAND detect program completion procedure.

5 . The memory device of claim 1 , wherein the power loss error detection procedure is based on a fail bit count associated with extra page data.

6 . The memory device of claim 1 , wherein the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio-dependent offset includes at least an offset associated with a Level 3 read reference voltage.

7 . The memory device of claim 1 , wherein the one or more components are further configured to determine the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio-dependent offset by using a look up table.

8 . The memory device of claim 1 , wherein the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio-dependent offset includes an offset in a range of approximately −40 millivolts (mV) to approximately −240 mV.

9 . A method, comprising:
determining, by a controller of a memory device, that a power loss has occurred; determining, by the controller of the memory device, a last written page (LWP) location associated with an LWP of a block of a memory of the memory device; determining, by the controller of the memory device, one of:
a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or
a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio; and
performing, by the controller of the memory device, a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage associated with the power loss error detection procedure.

10 . The method of claim 9 , further comprising:
determining, by the controller of the memory device, the WLG associated with the LWP location and the at least one WLG-dependent offset associated with the WLG; and performing, by the controller of the memory device, the power loss error detection procedure based at least in part on the at least one WLG-dependent offset.

11 . The method of claim 9 , further comprising:
determining, by the controller of the memory device, the PB fill ratio associated with the LWP location and the at least one PB-fill-ratio-dependent offset associated with the PB fill ratio; and performing, by the controller of the memory device, the power loss error detection procedure based on the at least one PB-fill-ratio-dependent offset.

12 . The method of claim 9 , wherein the power loss error detection procedure is associated with a NAND detect program completion procedure.

13 . The method of claim 9 , wherein the power loss error detection procedure is based on a fail bit count associated with extra page data.

14 . The method of claim 9 , wherein the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio-dependent offset includes at least an offset associated with a Level 3 read reference voltage.

15 . The method of claim 9 , further comprising determining, by the controller of the memory device, the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio-dependent offset by using a look up table.

16 . The method of claim 9 , wherein the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio-dependent offset includes an offset in a range of approximately −40 millivolts (mV) to approximately −240 mV.

17 . An apparatus, comprising:
means for determining that a power loss has occurred; means for determining a last written page (LWP) location associated with an LWP of a block of a memory associated with the apparatus; means for determining one of:
a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or
a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio; and
means for performing a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio-dependent offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage associated with the power loss error detection procedure.

18 . The apparatus of claim 17 , further comprising:
means for determining the WLG associated with the LWP location and the at least one WLG-dependent offset associated with the WLG; and means for performing the power loss error detection procedure based at least in part on the at least one WLG-dependent offset.

19 . The apparatus of claim 17 , further comprising:
means for determining the PB fill ratio associated with the LWP location and the at least one PB-fill-ratio-dependent offset associated with the PB fill ratio; and means for performing the power loss error detection procedure based on the at least one PB-fill-ratio-dependent offset.

20 . The apparatus of claim 17 , wherein the power loss error detection procedure is associated with a NAND detect program completion procedure.

Assignees

• Micron Technology Inc

Inventors

• Zhang Peng
• Lin Lei
• Xu Zhongguang
• Chang Li-Te
• Chen Zhengang
• Lang Murong
• Zhou Zhenming

Classifications

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title