Software visible and controllable lock-stepping with configurable logical processor granularities

Patent metadata

Field	Value
Publication number	US-12505000-B2
Application number	US-202418775652-A
Country	US
Kind code	B2
Filing date	Jul 17, 2024
Priority date	Dec 24, 2020
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.

First claim

What is claimed is:

1 . A processor comprising:
a control register field visible to software above a BIOS level, the control register field to specify a granularity of a processing entity of a lock-step group; and logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from a lock-step mode that is to include:
termination of lock-step execution by the lock-step group's processing entities before a program code, executed in lock-step, is fully executed; and,
as part of an exit from the lock-step mode, restoration of a state of a shadow processing entity of the lock-step group's processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.

2 . The processor of claim 1 , wherein the granularity is any of:
an instruction execution pipeline granularity; a module granularity; a tile granularity; a die granularity; or a core granularity.

3 . The processor of claim 1 , further comprising a second control register field to indicate that state information of the shadow processing entity of the lock step group's processing entities has been saved.

4 . The processor of claim 3 , wherein the control register field and the second control register field are assigned a class that permits the control register field and the second control register field to be accessed by at least one of a virtual machine monitor and an operating system.

5 . The processor of claim 4 , wherein the class permits the control register field and the second control register field to be accessed by a BIOS.

6 . The processor of claim 3 , further comprising a third control register field to provide information that describes an event that caused the termination of the lock-step execution of the program code.

7 . The processor of claim 6 , wherein the information is able to describe any of the following:
mis-compare during the lock-step execution of the program code; an interrupt has been received by a shadow processing entity of the lock-step group's processing entities; or a software initiated interrupt has occurred.

8 . The processor of claim 6 , further comprising a fourth control register field that, if a mis-compare during the lock-step execution of the program code caused the termination, provides even further information indicating any of:
the lock-step execution of the program code can be restarted without software curing a corrupted processing entity architectural state; the lock-step execution of the program code cannot be restarted without software curing corrupted processing entity architectural state; or the lock-step execution of the program code cannot be restarted.

9 . The processor of claim 8 , wherein the logic circuitry is to mark data processed by the lock-step group's processing entities as being poisoned.

10 . The processor of claim 8 , wherein the control register field, the second control register field, the third control register field and the fourth control register field are arranged to be maintained in one or more model specific registers.

11 . A computing system, comprising:
a processor, the processor comprising:
a control register field visible to software above a BIOS level, the control register field to specify a granularity of a processing entity of a lock-step group; and
logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from a lock-step mode that is to include:
termination of lock-step execution by the lock-step group's processing entities before a program code, executed in lock-step, is fully executed; and
as part of an exit from the lock-step mode, restoration of a state of a shadow processing entity of the lock-step group's processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code;

a main memory coupled to the processor; and a network interface.

12 . The computing system of claim 11 , wherein the granularity is any of:
an instruction execution pipeline granularity; a module granularity; a tile granularity; a die granularity; or a core granularity.

13 . The computing system of claim 11 , further comprising a second control register field to indicate that state information of the shadow processing entity of the lock step group's processing entities has been saved.

14 . The computing system of claim 13 , wherein the control register field and the second control register field are assigned a class that permits the control register field and the second control register field to be accessed by at least one of a virtual machine monitor and an operating system.

15 . The computing system of claim 14 , wherein the class permits the control register field and the second control register field to be accessed by a BIOS.

16 . The computing system of claim 13 , further comprising a third control register field to provide information that describes an event that caused the termination of the lock-step execution of the program code.

17 . The computing system of claim 16 , wherein the information is able to describe any of the following:
mis-compare during the lock-step execution of the program code; an interrupt has been received by a shadow processing entity of the lock-step group's processing entities; or a software initiated interrupt has occurred.

18 . The computing system of claim 16 , further comprising a fourth control register field that, if a mis-compare during the lock-step execution of the program code caused the termination, provides even further information indicating any of:
the lock-step execution of the program code can be restarted without software curing a corrupted processing entity architectural state; the lock-step execution of the program code cannot be restarted without software curing corrupted processing entity architectural state; or the lock-step execution of the program code cannot be restarted.

19 . The computing system of claim 18 , wherein the logic circuitry is to mark data processed by the lock-step group's processing entities as being poisoned.

20 . The computing system of claim 19 , wherein the control register field, the second control register field, the third control register field and the fourth control register field are arranged to be maintained in one or more model specific registers.

Assignees

• Intel Corp

Inventors

• Shanbhogue Vedvyas
• Huxel Jeff A
• Wiedemeier Jeffrey G
• Allen James D
• Raman Arvind
• Ganapathy Krishnakumar

Classifications

• G06F11/1629

  Error detection by comparing the output of redundant processing systems · CPC title

• G06F11/1683 Primary

  at instruction level · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title