Methods and apparatus to perform error detection and/or correction in a memory device

Patent metadata

Field	Value
Publication number	US-11080135-B2
Application number	US-201716617411-A
Country	US
Kind code	B2
Filing date	Jun 27, 2017
Priority date	Jun 27, 2017
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.

First claim

What is claimed is:

1. An apparatus to monitor memory, the apparatus comprising:
an error manager to:
compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations; and
update a first one of the counters corresponding to the first memory location in response to a first address of the first memory location matching a second address of one of the memory locations in the error history log;

a memory controller interface to:
monitor a change in a voltage level of a status pin based on a detection of the first memory location, the first memory location including a memory cell; and
obtain the first address of the first memory location after the voltage level of the status pin changes; and

a command generator to, in response to the first one of the counters satisfying a threshold, transmit a command to an error corrector to perform error correction on the first memory location.

2. The apparatus of claim 1 , wherein the error manager is to generate a second counter corresponding to the first memory location in response to the first address of the first memory location not matching the second address of one of the memory locations in the error history log.

3. An apparatus to monitor memory, the apparatus comprising:
an error manager to:
compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations; and
update a first one of the counters corresponding to the first memory location in response to a first address of the first memory location matching a second address of one of the memory locations in the error history log; and

a command generator to, in response to the first one of the counters satisfying a threshold, transmit a command to an error corrector to perform error correction on the first memory location, the error corrector to perform the error correction by using an adaptive double device data correction process.

4. An apparatus to monitor memory, the apparatus comprising:
an error manager to:
compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations; and
update a first one of the counters corresponding to the first memory location in response to a first address of the first memory location matching a second address of one of the memory locations in the error history log;

a command generator to, in response to the first one of the counters satisfying a threshold, transmit a command to an error corrector to perform error correction on the first memory location; and
an adaptive threshold manager to:
generate the threshold, the threshold is a first adaptive-time window threshold, the first adaptive-time window threshold variable over time based on changes in at least one of a utilization, a temperature, or an elevation of the memory; and
determine whether the first error is a random error or a persistent error based on whether the first one of the counters satisfies the first adaptive-time window threshold.

5. The apparatus of claim 4 , wherein the first adaptive-time window threshold is based on a time difference between consecutive errors or a total number of errors within a time window.

6. The apparatus of claim 4 , wherein the adaptive threshold manager is to compare a second one of the counters to a second adaptive-time window threshold, the second adaptive-time window threshold different from the first adaptive-time window threshold.

7. An apparatus to monitor memory, the apparatus comprising:
means for comparing to:
compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations; and
update a first one of the counters corresponding to the first memory location in response to a first address of the first memory location matching a second address of one of the memory locations in the error history log;

means for monitoring a change in a voltage level of a status pin based on a detection of the first memory location, the first memory location including a memory cell;
means for obtaining the first address of the first memory location after the voltage level of the status pin changes; and
means for transmitting a command to a means for performing error correction on the first memory location, the transmitting of the command in response to the first one of the counters satisfying a threshold.

8. The apparatus of claim 7 , wherein the means for comparing is to generate a second counter corresponding to the first memory location in response to the first address of the first memory location not matching the second address of one of the memory locations in the error history log.

9. An apparatus to monitor memory, the apparatus comprising:
means for comparing to:
compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations; and
update a first one of the counters corresponding to the first memory location in response to a first address of the first memory location matching a second address of one of the memory locations in the error history log; and

means for transmitting a command to a means for performing error correction on the first memory location, the transmitting of the command in response to the first one of the counters satisfying a threshold, the means for performing error correction is to perform the error correction by using an adaptive double device data correction process.

10. An apparatus to monitor memory, the apparatus comprising:
means for comparing to:
compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations; and
update a first one of the counters corresponding to the first memory location in response to a first address of the first memory location matching a second address of one of the memory locations in the error history log;

means for transmitting a command to a means for performing error correction on the first memory location, the transmitting of the command in response to the first one of the counters satisfying a threshold; and
means for generating to:
generate the threshold, the threshold is a fir

Assignees

• Intel Corp

Inventors

• Chen Yingwen
• Agrawal Anil
• Yuan Fang
• Huang Qing

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G01R31/31713

  Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572) · CPC title