SRAM cell structure

Patent metadata

Field	Value
Publication number	US-12501600-B2
Application number	US-202217588509-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Oct 4, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A SRAM cell structure includes a plurality of transistors, a set of contacts, a word-line, a bit-line, a VDD contacting line and a VSS contacting line. The plurality of transistors include n transistors, wherein n is a positive integral less than 6. The set of contacts are coupled to the plurality of transistors. The word-line is electrically coupled to the plurality of transistors. The bit-line and a bit line bar are electrically coupled to the plurality of transistors. The VDD contacting line is electrically coupled to the plurality of transistors. The VSS contacting line is electrically coupled to the plurality of transistors. Wherein as a minimum feature size of the SRAM cell structure gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of the minimum feature size (λ) is the same or substantially the same.

First claim

What is claimed is:

1 . A SRAM cell structure, comprising:
a substrate, having an original horizontal surface; a plurality of transistors including n transistors formed in the substrate, wherein n is a positive integral less than 6; wherein one of the n transistors comprises a gate structure, a source region and, a drain region and a localized isolation extending under the source region or the drain region but not extending under the gate structure, and a shallow trench isolation (STI) region surrounds the one transistor; wherein a top surface of the STI region is higher than the original horizontal surface; a set of contacts coupled to the plurality of transistors; a word-line electrically coupled to the plurality of transistors; a bit-line and a bit line bar electrically coupled to the plurality of transistors; a VDD contacting line electrically coupled to the plurality of transistors; a tunneling structure disposed between the VDD contacting line and the plurality of transistors; and a VSS contacting line electrically coupled to the plurality of transistors; wherein as a minimum feature size of the SRAM cell structure is between 28 nm and 20 nm, an area size of the SRAM cell structure in terms of square of the minimum feature size (λ) is less than 100λ 2 ; or as the minimum feature size of the SRAM cell structure less than 20 nm and not less than 10 nm, the area size of the SRAM cell structure in terms of square of the minimum feature size (λ) is less than 200λ 2 ; or as the minimum feature size of the SRAM cell structure less than 10 nm and not less than 5 nm, the area size of the SRAM cell structure in terms of square of the minimum feature size (λ) is less than 300λ 2 .

2 . The SRAM cell structure according to claim 1 , wherein when A is decreased from 28 nm to 5 nm, the area size of the SRAM cell is between 51λ 2 ˜102λ 2 .

3 . The SRAM cell structure according to claim 2 , wherein a length of a first transistor in the plurality of transistors is between 3˜5λ 2 .

4 . The SRAM cell structure according to claim 1 ,
wherein the tunneling structure includes a first dielectric layer with a thickness of a monolayer and 10 nm.

5 . The SRAM cell structure according to claim 4 , wherein the first dielectric layer is between the VDD contacting line and another metal layer to form a MIM structure.

6 . A SRAM cell structure, comprising:
a substrate, having an original horizontal surface; a pair of cross-coupled transistors formed in the substrate, wherein one of the pair of cross-coupled transistors comprises a gate structure, a source region and, a drain region and a localized isolation extending under the source region or the drain region but not extending under the gate structure, and a shallow trench isolation (STI) region surrounds the source region and the drain region; wherein a top surface of the STI region is higher than the original horizontal surface; a VDD contacting line, electrically coupled to the pair of cross-coupled transistors; a VSS contacting line, electrically coupled to the pair of cross-coupled transistors; and a tunneling structure disposed between the VDD contacting line and pair of cross-coupled transistors; wherein the tunneling structure is a two-terminals device with bilateral current directions.

7 . The SRAM cell structure according to claim 6 , wherein the VDD contacting line is electrically coupled to the pair of cross-coupled transistors through the tunneling structure based on tunneling effect.

8 . The SRAM cell structure according to claim 6 , wherein the tunneling structure includes a first dielectric layer made of boron nitride, CaF 2 , SiO 2 , HfO 2 , Ta 2 O 5 , or Perylene-3,4,9,10-tetracarboxylic dianhydride (PTCDA), and wherein a thickness of the first dielectric layer is between a thickness of a monolayer and 10 nm.

9 . The SRAM cell structure according to claim 6 , wherein the tunneling structure includes a superlattice structure with well layers sandwiched by barrier layers.

10 . The SRAM cell structure according to claim 9 , wherein the thickness of the well layers or the barrier layers are modulated or gradually changed from one side of the tunneling structure to the other side of the tunneling structure.

11 . The SRAM cell structure according to claim 9 , wherein the thickness of the superlattice structure is less than 20 nm.

12 . The SRAM cell structure according to claim 9 , the material composition of the well layers are modulated or gradually changed from one side of the tunneling structure to the other side of the tunneling structure.

13 . The SRAM cell structure according to claim 9 , the doping concentration of the well layers are modulated or gradually changed from one side of the tunneling structure to the other side of the tunneling structure.

14 . The SRAM cell structure according to claim 6 , further comprising:
a first passing transistor; a second passing transistor; a word-line, electrically coupled to the first passing transistor and the second passing transistor; a bit-line; and a bit line bar, electrically coupled to the first passing transistor and the second passing transistor, respectively.

15 . A SRAM cell structure, comprising:
a substrate, having an original horizontal surface; a plurality of transistors including n transistors within the substrate, wherein n is a positive integral less than 6; wherein one of the n transistors comprises a source region and a drain region, and a shallow trench isolation (STI) region surrounds the source region and the drain region; wherein a top surface of the STI region is higher than the original horizontal surface; a plurality of contacts coupled to the plurality of transistors; a set of first metal layers disposed above and electrically coupled to the plurality of transistors; a set of second metal layers disposed above the set of first metal layers and electrically coupled to the plurality of transistors; and a metal-insulator-metal (MIM) structure above the plurality of transistors comprising a tunneling dielectric layer covering the a surface of the a metal-1 layer: wherein the plurality of contacts comprise a set of first contacts and a set of second contacts, the set of first contacts are connected to the set of first metal layers, and the set of second contacts are connected to the set of second metal layers but disconnected from the set of first metal layers; wherein a bottom surface of an n+ region of a first transistor in the plurality of transistors is fully isolated by a first insulator, and the first insulator comprises a L-shaped oxide layer.

16 . The SRAM cell structure according to claim 15 ,
wherein the tunneling dielectric layer is made of hexagonal boron nitride (hBN) with a thickness between a monolayer and 10 nm.

17 . A SRAM cell structure, comprising:
a substrate, having an original horizontal surface; a plurality of transistors, including n transistors formed in the substrate, wherein n is a positive integral less than 6, wherein a first transistor of the plurality of transistors comprises: a gate structure with a length; a channel region; a first conductive region, electrically coupled to the channel region; and a first contact hole, positioned above the first conductive region; a second conductive region, electrically coupled to the channel region; and a shallow trench isolation (STI) region surrounding the first conductive region and the second conductive region; wherein a top surface of the STI region is higher than the original horizontal surface; and a localized iso

Assignees

• Invent And Collaboration Laboratory Pte Ltd
• Etron Tech Inc

Inventors

• Lu chao-chun
• Huang Li-Ping
• Chueh Juang-Ying

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10D8/70

  Tunnel-effect diodes · CPC title

• Y10S257/903

  FET configuration adapted for use as static memory cell · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title

• H10B10/18

  Peripheral circuit regions · CPC title