Semiconductor storage device using stt-mram

Patent metadata

Field	Value
Publication number	US-2016372174-A1
Application number	US-201415101809-A
Country	US
Kind code	A1
Filing date	Dec 3, 2014
Priority date	Dec 5, 2013
Publication date	Dec 22, 2016
Grant date	—

Abstract

A memory circuit ( 100 ) includes a plurality of memory cells ( 50 ), an N-type MOSFET ( 30 a ) and an N-type MOSFET ( 30 b ). The drain of the N-type MOSFET ( 30 a ) is connected to one of a pair of bit lines, and the drain of the N-type MOSFET ( 30 b ) is connected to the other of the pair of bit lines. The gate of the N-type MOSFET ( 30 a ) is connected to the drain of the N-type MOSFET ( 30 b ), and the gate of the N-type MOSFET ( 30 b ) is connected to the drain of the N-type MOSFET ( 30 a ).

First claim

1 . A semiconductor memory device comprising:
a plurality of memory cells, each comprising a first MOSFET and a first MTJ serially connected thereto, arranged between one of a pair of bit lines and one of a pair of source lines, a second MOSFET and a second MTJ serially connected thereto, arranged between other of the pair of bit lines and other of the pair of source lines; a third MOSFET; and a fourth MOSFET; wherein the drain of the third MOSFET is connected to one of the pair of bit lines, the drain of the fourth MOSFET is connected to the other of the pair of bit lines, the gate of the third MOSFET is connected to the drain of the fourth MOSFET and the gate of the fourth MOSFET is connected to the drain of the third MOSFET.

2 . The semiconductor memory device according to claim 1 , wherein the first MOSFET and the second MOSFET are MOSFETs of a first conduction type, and the third MOSFET and the fourth MOSFET are MOSFETs of a second conduction type differing from the first conduction type.

3 . The semiconductor memory device according to claim 2 , wherein:
the drain of the third MOSFET is connected to one of the pair of bit lines via a fifth MOSFET, and the drain of the fourth MOSFET is connected to the other of the pair of bit lines via a sixth MOSFET; and the fifth MOSFET and the sixth MOSFET are MOSFETs of the second conduction type.

4 . The semiconductor memory device according to claim 2 , wherein:
the sources of the third MOSFET and the fourth MOSFET are connected to a first common node, and the first common node is connected to a ground voltage or a power source voltage via a seventh MOSFET; and the seventh MOSFET is a MOSFET of the second conduction type.

5 . The semiconductor memory device according to claim 2 , wherein:
the drain of an eighth MOSFET is connected to the drain of the third MOSFET, the drain of a ninth MOSFET is connected to the drain of the fourth MOSFET, the drain of the eighth MOSFET is connected to the gate of the ninth MOSFET, and the drain of the ninth MOSFET is connected to the gate of the eighth MOSFET; and the eighth MOSFET and the ninth MOSFET are MOSFETs of the first conduction type.

6 . The semiconductor memory device according to claim 5 wherein:
the sources of the eighth MOSFET and the ninth MOSFET are connected to a second common node, and the second common node is connected to a power source voltage or a ground voltage via a tenth MOSFET; and
the tenth MOSFET is a MOSFET of the first conduction type.

7 . The semiconductor memory device according to claim 6 , wherein when the tenth MOSFET turns on, the first MOSFET and the second MOSFET turn off.

8 . The semiconductor memory device according to claim 3 wherein:
the drain of an eighth MOSFET is connected to the drain of the third MOSFET, the drain of a ninth MOSFET is connected to the drain of the fourth MOSFET, the drain of the eighth MOSFET is connected to the gate of the ninth MOSFET, and the drain of the ninth MOSFET is connected to the gate of the eighth MOSFET;
the eighth MOSFET and the ninth MOSFET are MOSFETs of the first conduction type;
the sources of the eighth MOSFET and the ninth MOSFET are connected to a second common node, and the second common node is connected to a power source voltage or a ground voltage via a tenth MOSFET;
the tenth MOSFET is a MOSFET of the first conduction type; and
when the tenth MOSFET turns on, the fifth MOSFET and the sixth MOSFET turn off.

9 . The semiconductor memory device according to claim 10 , wherein:
the pair of source lines is connected to a power source voltage or a ground voltage via an eleventh MOSFET and a twelfth MOSFET, respectively; and the eleventh MOSFET and the twelfth MOSFET are MOSFETs of the first conduction type.

10 . The semiconductor memory device according to claim 3 , further comprising:
a thirteenth MOSFET and a fourteenth MOSFET are connected in parallel with the fifth and the sixth MOSFETs, respectively; and wherein the thirteenth and the fourteenth MOSFETs are MOSFETs of the first conduction type.

11 . The semiconductor memory device according to claim 10 , wherein:
the sources of the third MOSFET and the fourth MOSFET are connected to a first common node, and the first common node is connected to a ground voltage or a power source voltage via a seventh MOSFET; and the seventh MOSFET is a MOSFET of the second conduction type.

12 . The semiconductor memory device according to claim 11 , wherein:
the drain of an eighth MOSFET is connected to the drain of the third MOSFET, the drain of a ninth MOSFET is connected to the drain of the fourth MOSFET, the drain of the eighth MOSFET is connected to the gate of the ninth MOSFET, and the drain of the ninth MOSFET is connected to the gate of the eighth MOSFET; and the eighth MOSFET and the ninth MOSFET are MOSFETs of the first conduction type.

Assignees

• Univ Tohoku

Inventors

• Ohsawa Takashi
• Endoh Tetsuo

Classifications

• G11C11/1697

  Power supply circuits · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G11C14/0081

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title