Substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength, and related IC packages and fabrication methods

Patent metadata

Field	Value
Publication number	US-12500146-B2
Application number	US-202318303072-A
Country	US
Kind code	B2
Filing date	Apr 19, 2023
Priority date	Apr 19, 2023
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength. In one aspect, a substrate comprises a core layer. The core layer comprises a metal core, the metal core having a first surface and a second surface opposite the first surface. The core layer further comprises a first insulation layer on the first surface and a second insulation layer on the second surface. The substrate further comprises a first metallization structure adjacent to the first insulation layer and a second metallization structure adjacent to the second insulation layer. The metal core provides electrical shielding of signals/power routed through the metal core for noise coupling reduction allowing a higher density of signal and power paths to be supported in substrate, while also strengthening structural integrity to prevent or reduce warpage in the IC package.

First claim

What is claimed is:

1 . A substrate, comprising:
a core layer comprising:
a metal core comprising a first surface and a second surface opposite the first surface;
a first insulation layer on the first surface; and
a second insulation layer on the second surface;
a first metallization structure adjacent to the first insulation layer; and a second metallization structure adjacent to the second insulation layer, wherein the first metallization structure further comprises:
a first metal blind via extending from a second metallization layer of the first metallization structure directly through a third metallization layer and a fourth metallization layer of the first metallization structure to the metal core; and
a second metal blind via extending from a first metallization layer directly through the second metallization layer of the first metallization structure to the metal core.

2 . The substrate of claim 1 , wherein:
the core layer extends in a first direction; and the core layer further comprises:
a metal via extending in a second direction and surrounded by insulation, the metal via coupling the first metallization structure with the second metallization structure.

3 . The substrate of claim 2 , wherein the metal via couples a first metallization layer in the first metallization structure with a first metallization layer in the second metallization structure.

4 . The substrate of claim 2 , wherein the metal via couples a second metallization layer in the first metallization structure with a first metallization layer in the second metallization structure.

5 . The substrate of claim 2 , wherein the metal core comprises a ground plane.

6 . The substrate of claim 5 , wherein the metal via comprises a power rail.

7 . The substrate of claim 1 , wherein the first metal blind via is configured to carry an electrical signal.

8 . The substrate of claim 1 comprising a package substrate.

9 . The substrate of claim 1 comprising an interposer substrate.

10 . The substrate of claim 1 integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; and an avionics system.

11 . A method for fabricating a substrate, comprising: forming a core layer, the core layer comprising: a metal core comprising a first surface and a second surface opposite the first surface; a first insulation layer on the first surface; and a second insulation layer on the second surface; forming a first metallization structure adjacent to the first insulation layer; and forming a second metallization structure adjacent to the second insulation layers forming a first metal blind via extending from a second metallization layer of the first metallization structure directly through a third metallization layer and a fourth metallization layer of the first metallization structure and terminating at the metal core and, forming a second metal blind via extending from a first metallization layer directly through the second metallization layer in the first metallization structure to the metal core.

12 . The method of claim 11 , wherein:
the core layer extends in a first direction; and the method further comprises:
forming a metal via extending in a second direction surrounded by insulation and coupling the first metallization structure with the second metallization structure.

13 . The method of claim 12 , further comprising:
coupling a first metallization layer in the first metallization structure with a first metallization layer in the second metallization structure through the metal via.

14 . The method of claim 12 , further comprising:
coupling a second metallization layer in the first metallization structure with a first metallization layer in the second metallization structure through the metal via.

15 . The method of claim 12 , further comprising:
coupling the metal core to electrical ground.

16 . The method of claim 12 , further comprising:
coupling the metal via to a power rail or an electrical signal.

17 . The method of claim 11 , further comprising:
coupling a first die to the substrate through die interconnects.

18 . The method of claim 17 , further comprising:
coupling a second die to the substrate through an interposer substrate and vertical interconnects.

19 . The method of claim 18 , further comprising:
coupling the first die on a package substrate through the die interconnects; and coupling the first die to the substrate through the package substrate and vertical interconnects.

20 . The method of claim 19 , further comprising:
coupling the second die to the substrate; and coupling the second die to the first die through the substrate, the vertical interconnects, and the package substrate.

21 . An (IC) package comprising:
a substrate for the IC package, comprising:
a core layer comprising:
a metal core, the metal core having a first surface and a second surface opposite the first surface;
a first insulation layer on the first surface; and
a second insulation layer on the second surface;

a first metallization structure adjacent to the first insulation layer; a second metallization structure adjacent to the second insulation layer; a first die coupled to the substrate through die interconnects; a plurality of vertical interconnects; an interposer substrate; a second die coupled to the substrate through the interposer substrate and the plurality of vertical interconnects; a package substrate; and a second die coupled to the package substrate and coupled to the first die through the substrate.

22 . The IC package of claim 21 , wherein:
the core layer extends in a first direction; and the core layer further comprises:
a metal via extending in a second direction surrounded by insulation and coupling the first metallization structure with the second metallization structure.

23 . The IC package of claim 22 , wherein the metal via couples a first metallization layer in the first metallization structure with a first metallization layer in the second metallization structure.

Assignees

• Qualcomm Inc

Inventors

• Kim Michelle Yejin
• We Hong Bok
• Buot Joan Rey Villarba
• Kang Kuiwon

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W70/6875 Primary

  being on a metallic substrate, e.g. insulated metal substrates [IMS] · CPC title