Semiconductor devices

Patent metadata

Field	Value
Publication number	US-12495597-B2
Application number	US-202318392870-A
Country	US
Kind code	B2
Filing date	Dec 21, 2023
Priority date	Jul 23, 2019
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate including a PMOS transistor region and a NMOS transistor region; a first gate structure on the PMOS transistor region of the substrate, the first gate structure including an interfacial insulation pattern, a gate insulation pattern including a metal oxide, a first threshold voltage controlling metal pattern, a second threshold voltage controlling metal pattern, and a polysilicon pattern stacked, the gate insulation pattern directly contacting the first threshold voltage controlling metal pattern; and a second gate structure on the NMOS transistor region of the substrate, the second gate structure including the interfacial insulation pattern, the gate insulation pattern including the metal oxide, the second threshold voltage controlling metal pattern, and the polysilicon pattern stacked; wherein the first gate structure and the second gate structure contacts a surface of the substrate.

2 . The semiconductor device of claim 1 , wherein the first threshold voltage controlling metal pattern includes titanium nitride.

3 . The semiconductor device of claim 1 , wherein the first threshold voltage controlling metal pattern has a thickness less than 100 Å.

4 . The semiconductor device of claim 1 , wherein the second threshold voltage controlling metal pattern has a lanthanum pattern and a titanium nitride layer pattern stacked.

5 . The semiconductor device of claim 1 , wherein, in the first and second gate structures, first dopants are within and at at least one surface of the gate insulation pattern and at an upper surface of the interfacial insulation pattern contacting the gate insulation pattern, and the first dopants include at least fluorine.

6 . The semiconductor device of claim 1 , wherein, in the first and second gate structures, the polysilicon pattern directly contacts the second threshold voltage controlling metal pattern, and the polysilicon pattern is doped with N-type or P-type impurities.

7 . The semiconductor device of claim 1 , wherein the first gate structure and the second gate structure have different stacked structures.

8 . The semiconductor device of claim 1 , wherein the substrate includes silicon substrate.

9 . A semiconductor device, comprising:
a substrate including a PMOS transistor region and a NMOS transistor region; a first gate structure on the PMOS transistor region of the substrate, the first gate structure including an interfacial insulation pattern, a gate insulation pattern including a metal oxide, a first threshold voltage controlling metal pattern, a second threshold voltage controlling metal pattern, a lower polysilicon pattern and a polysilicon pattern stacked; and a second gate structure on the NMOS transistor region of the substrate, the second gate structure including the interfacial insulation pattern, the gate insulation pattern including the metal oxide, the second threshold voltage controlling metal pattern, the lower polysilicon pattern and the polysilicon pattern stacked; wherein, in the first and second gate structures, first dopants are within and at at least one surface of the gate insulation pattern and at an upper surface of the interfacial insulation pattern contacting the gate insulation pattern, and the first dopants include at least fluorine.

10 . The semiconductor device of claim 9 , wherein, in the first and second gate structures,
the lower polysilicon pattern contacts the second threshold voltage controlling metal pattern, and the lower polysilicon pattern includes second dopants including at least fluorine; and the polysilicon pattern is formed on the lower polysilicon pattern, the polysilicon pattern is doped with N-type or P-type impurities.

11 . The semiconductor device of claim 9 , wherein the first gate structure and the second gate structure have different stacked structures.

12 . The semiconductor device of claim 9 , wherein the substrate includes silicon substrate.

13 . The semiconductor device of claim 9 , wherein the first gate structure and the second gate structure contacts a surface of the substrate.

14 . The semiconductor device of claim 9 , wherein the first threshold voltage controlling metal pattern includes titanium nitride.

15 . The semiconductor device of claim 9 , wherein the first threshold voltage controlling metal pattern has a thickness less than 100 Å.

16 . The semiconductor device of claim 9 , wherein the second threshold voltage controlling metal pattern has a lanthanum pattern and a titanium nitride layer pattern stacked.

Assignees

• Samsung Electronics Co Ltd

Inventors

• An Hokyun
• Kim Bumsoo
• Kim Hyunseung
• Jiao Guangfan

Classifications

• H10P32/20

  Diffusion for doping of insulating layers · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D84/83135

  the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title

• H10D64/669

  the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN · CPC title