Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same

Patent metadata

Field	Value
Publication number	US-9634011-B2
Application number	US-201514937056-A
Country	US
Kind code	B2
Filing date	Nov 10, 2015
Priority date	Apr 22, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a trench;
a gate dielectric layer formed over a surface of the trench;
a first impurity region and a second impurity region formed in the substrate separated from each other by the trench;
a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion;
a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and
a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer,
wherein the dielectric work function adjusting liner is formed over the lower portion of the trench without overlapping with the first and the second impurity region.

2. The semiconductor device according to claim 1 ,
wherein the upper buried portion has a first work function, and
wherein the dipole formed by the dielectric work function adjusting liner induces a second work function higher than the first work function.

3. The semiconductor device according to claim 1 ,
wherein the lower buried portion has a first high work function higher than that of the upper buried portion, and
wherein the dipole formed by the dielectric work function adjusting liner induces a second high work function higher than the first high work function.

4. The semiconductor device according to claim 1 , wherein the dielectric work function adjusting liner comprises a high oxygen containing-metal oxide which has oxygen content per unit volume greater than that of the gate dielectric layer.

5. The semiconductor device according to claim 1 ,
wherein the gate dielectric layer comprises silicon oxide (SiO 2 ), and
wherein the dielectric work function adjusting liner comprises aluminum oxide (Al 2 O 3 ).

6. The semiconductor device according to claim 1 ,
wherein the gate dielectric layer comprises silicon oxide (SiO 2 ), and
wherein the dielectric work function adjusting liner comprises one or more of titanium oxide (TiO 2 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ) and magnesium oxide (MgO).

7. The semiconductor device according to claim 1 , wherein the upper buried portion comprises N-type doped polysilicon.

8. The semiconductor device according to claim 1 , wherein the lower buried portion comprises a material which has a resistivity lower than that of the upper buried portion.

9. The semiconductor device according to claim 1 , wherein the lower buried portion comprises one or more of a metal material which is non-reactive with the upper buried portion and a metal material which is reactive with the upper buried portion.

10. The semiconductor device according to claim 1 ,
further comprising an intermediate barrier between the lower buried portion and the upper buried portion,
wherein the lower buried portion comprises a metal material which is reactive with the upper buried portion.

11. The semiconductor device according to claim 1 ,
further comprising:
an intermediate barrier between the lower buried portion and the upper buried portion; and
a lower barrier between the lower buried portion and the dielectric work function adjusting liner,
wherein the lower buried portion comprises a metal material that is reactive with the upper buried portion and does not contain fluorine.

12. The semiconductor device according to claim 1 , further comprising a fin formed in the substrate under the lower buried portion, with the gate dielectric layer interposed therebetween.

13. The semiconductor device according to claim 1 ,
wherein the first impurity region and the second impurity region are formed in the substrate on both sides of the gate electrode, and
wherein the first impurity region and the second impurity region have a depth overlapping the upper buried portion.

Assignees

• Sk Hynix Inc

Inventors

• Kang Dong-Kyun
• Cho Ho-Jin

Classifications

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title

• H10P14/69394

  the material containing titanium, e.g. TiO2 · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6939

  characterised by the metal · CPC title