Semiconductor packages having fixing members

Patent metadata

Field	Value
Publication number	US-12494439-B2
Application number	US-202318107143-A
Country	US
Kind code	B2
Filing date	Feb 8, 2023
Priority date	Feb 16, 2022
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A semiconductor package includes an interposer including an upper pad and an upper passivation layer partially covering the upper pad, a semiconductor chip disposed on the interposer, a conductor pattern disposed on the interposer, a guide pattern disposed on the interposer while including a main opening and at least one sub-opening connected to the main opening, a support disposed on the interposer while including a core portion and a peripheral portion surrounding the core portion, a lower surface of the support being disposed in the main opening of the guide pattern, an upper redistribution structure disposed on the semiconductor chip and connected to the conductor pattern and the guide pattern, and an encapsulant between the interposer and the upper redistribution structure. The encapsulant contacts an inner wall of the main opening, an inner wall of the at least one sub-opening and a side surface of the support.

First claim

What is claimed is:

1 . A semiconductor package comprising:
an interposer comprising an upper pad and an upper passivation layer partially covering the upper pad; a semiconductor chip disposed on the interposer; a conductor pattern disposed on the interposer and contacting the upper pad; a first guide pattern disposed on the interposer, the first guide pattern comprising a main opening and at least one sub-opening connected to the main opening; a first support disposed on the interposer, the first support comprising a core portion and a peripheral portion surrounding the core portion, and a lower surface of the first support being disposed in the main opening of the first guide pattern; an upper redistribution structure disposed on the semiconductor chip and contacting the conductor pattern and the first guide pattern; and an encapsulant between the interposer and the upper redistribution structure, wherein the encapsulant contacts an inner wall of the main opening, an inner wall of the at least one sub-opening and a side surface of the first support.

2 . The semiconductor package according to claim 1 , wherein the at least one sub-opening protrudes from the main opening in a horizontal direction.

3 . The semiconductor package according to claim 1 , wherein the peripheral portion comprises a solder, and the core portion comprises at least one of nickel and copper.

4 . The semiconductor package according to claim 1 , wherein the lower surface of the first support contacts an upper surface of the upper passivation layer.

5 . The semiconductor package according to claim 1 , wherein:
an upper surface of the first support is disposed at a same level as an upper surface of the conductor pattern; and the lower surface of the first support is disposed at a higher level than a lower surface of the conductor pattern.

6 . The semiconductor package according to claim 1 , wherein the at least one sub-opening comprises a plurality of sub-openings disposed to be spaced apart from one another by a uniform distance along a circumference of the main opening.

7 . The semiconductor package according to claim 1 , wherein the at least one sub-opening comprises a plurality of sub-openings symmetrically disposed with respect to the main opening.

8 . The semiconductor package according to claim 7 , wherein the plurality of sub-openings extends in the same direction.

9 . The semiconductor package according to claim 1 , wherein the at least one sub-opening has a length of 12 μm or more and a width of 50 to 120 μm.

10 . The semiconductor package according to claim 1 , wherein the at least one sub-opening comprises a sub-opening through which the main opening communicates with an exterior of the first guide pattern.

11 . The semiconductor package according to claim 1 , further comprising:
a second guide pattern disposed adjacent to the first guide pattern; and a second support disposed adjacent to the first support, wherein the first guide pattern comprises a first main opening, and the second guide pattern comprises a second main opening, and wherein the first support is disposed in the first main opening, and a second support is disposed in the second main opening.

12 . The semiconductor package according to claim 11 , wherein the first guide pattern comprises a sub-opening through which the first main opening communicates with an exterior of the first guide pattern.

13 . The semiconductor package according to claim 1 , further comprising:
a second support disposed adjacent to the first support, wherein the first guide pattern comprises a first main opening in which the first support is disposed, and a second main opening in which the second support is disposed.

14 . The semiconductor package according to claim 13 , wherein the first guide pattern comprises a connection passage interconnecting the first main opening and the second main opening.

15 . The semiconductor package according to claim 1 , wherein:
the upper passivation layer comprises a recessed region formed along the main opening; the lower surface of the first support contacts a bottom surface of the recessed region; and the encapsulant contacts the bottom surface of the recessed region.

16 . The semiconductor package according to claim 15 , wherein the recessed region further extends along the at least one sub-opening.

17 . A method for manufacturing a semiconductor package, comprising:
providing an interposer comprising, at an upper surface thereof, an upper pad and an upper passivation layer partially covering the upper pad; forming, on the interposer, an insulating material to cover the upper passivation layer; patterning the insulating material, thereby forming a guide pattern comprising, therein, a main opening and at least one sub-opening connected to the main opening; mounting a semiconductor chip on the interposer; stacking an upper redistribution structure connected to a conductor pattern and a support on the interposer and the semiconductor chip, a lower surface of the support being disposed in the main opening; and forming an encapsulant to cover the semiconductor chip, the conductor pattern and the support.

18 . The method according to claim 17 , wherein the encapsulant covers an inner wall of the main opening, an inner wall of the at least one sub-opening and a side surface of the support.

19 . A semiconductor package comprising:
a lower package; and an upper package on the lower package, wherein the lower package comprises:
an interposer comprising an upper pad and an upper passivation layer partially covering the upper pad;
a lower semiconductor chip disposed on the interposer;
a conductor pattern disposed on the interposer and contacting the upper pad;
a guide pattern disposed on the interposer, the guide pattern comprising a main opening and at least one sub-opening connected to the main opening;
a support disposed on the interposer, the support comprising a core portion and a peripheral portion surrounding the core portion, and a lower surface of the support being disposed in the main opening of the guide pattern;
an upper redistribution structure disposed on the lower semiconductor chip and contacting the conductor pattern and the guide pattern; and
an encapsulant between the interposer and the upper redistribution structure,
wherein the encapsulant contacts an inner wall of the main opening, an inner wall of the at least one sub-opening, and a side surface of the support.

20 . The semiconductor package according to claim 19 , wherein:
the upper package comprises:
a substrate;
a package connection terminal disposed under the substrate and electrically connected to the upper redistribution structure; and
an upper semiconductor chip on the substrate; and
the upper semiconductor chip is electrically connected to the upper redistribution structure via the substrate and the package connection terminal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yongkwan
• Kim Seunghwan
• Kim Jungjoo
• Kim Jongwan
• Park Junwoo
• Baek Hyunggil
• Lee Junga

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W46/301

  for alignment · CPC title