Integration scheme to build resistor, capacitor, efuse using silicon-rich dielectric layer as a base dielectric

Patent metadata

Field	Value
Publication number	US-12494425-B2
Application number	US-202117489910-A
Country	US
Kind code	B2
Filing date	Sep 30, 2021
Priority date	May 21, 2021
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A method and an electronic device that includes an isolation structure having a dielectric material on or in a semiconductor surface layer, and a passive circuit component having a metal silicide structure on a side of the isolation structure, there the metal silicide structure includes a metal silicide portion and a dielectric portion, the dielectric portion of the metal silicide structure including one of silicon nitride, silicon oxide, silicon carbide, silicon carbon nitride, and silicon oxynitride. The method includes forming a dielectric material of the isolation structure on or in the semiconductor surface layer, forming a silicon-rich dielectric layer on a side of the isolation structure, and siliciding the silicon-rich dielectric layer to form the metal silicide structure on the side of the isolation structure.

First claim

What is claimed is:

1 . A method of forming a passive circuit component, the method comprising:
forming an isolation structure extending into a semiconductor surface layer of a substrate; forming a silicon-rich dielectric layer on a side of the isolation structure, the silicon-rich dielectric layer selected from a first group consisting of silicon-rich nitride, silicon-rich oxide, and silicon-rich carbide; siliciding the silicon-rich dielectric layer to form a metal silicide structure of the passive circuit component; forming a dielectric layer over the semiconductor surface layer, the isolation structure, and the metal silicide structure; forming a conductive contact through the dielectric layer to contact the metal silicide structure; and forming a metallization structure over the dielectric layer to couple the metal silicide structure to a circuit.

2 . The method of claim 1 , wherein: the silicon-rich dielectric layer is one of a silicon-rich nitride material, a silicon-rich carbon nitride material, and a silicon-rich oxynitride material having a silicon-to-nitrogen atomic ratio of approximately 1.5 to 10 as measured by an elemental analysis technique.

3 . The method of claim 1 , wherein the silicon-rich dielectric layer is a silicon-rich oxide material or a silicon-rich oxynitride material having a silicon-to-oxygen atomic ratio of approximately 1.0 to 10 as measured by an elemental analysis technique.

4 . The method of claim 1 , wherein the silicon-rich dielectric layer is a silicon-rich carbide material or a silicon-rich carbon nitride material having a silicon-to-carbon atomic ratio of approximately 1.5 to 10 as measured by an elemental analysis technique.

5 . The method of claim 1 , wherein the isolation structure is a shallow trench isolation (STI) structure.

6 . The method of claim 1 , wherein the passive circuit component is a resistor.

7 . The method of claim 1 , wherein the passive circuit component is a capacitor.

8 . The method of claim 1 , wherein the passive circuit component is a fuse.

9 . A method of forming an electronic device, the method comprising:
forming a dielectric material of an isolation structure on or in a semiconductor surface layer; forming a material stack on a side of the isolation structure, including:
performing a deposition process that deposits a silicon-rich dielectric layer on the dielectric material of the isolation structure,
depositing an oxynitride layer on the silicon-rich dielectric layer,
depositing a polysilicon layer on the oxynitride layer, and
patterning the polysilicon layer, the oxynitride layer, and the silicon-rich dielectric layer;
siliciding the silicon-rich dielectric layer to form a metal silicide structure of a passive circuit component on the side of the isolation structure, the siliciding including:
performing a second deposition process that deposits a silicidable metal layer over the material stack, and
annealing the material stack and the silicidable metal layer thereby forming the metal silicide structure on the side of the isolation structure; and
removing substantially all unreacted metal from the metal silicide structure.

10 . The method of claim 9 , wherein the silicon-rich dielectric layer is a stress memorization technique (SMT) layer.

11 . The method of claim 9 , wherein the second deposition process deposits the silicidable metal layer directly on the patterned silicon-rich dielectric layer.

12 . The method of claim 11 , wherein:
the second deposition process deposits the silicidable metal layer on a gate and a source/drain on or in the semiconductor surface layer; and the annealing the material stack and the silicidable metal layer concurrently:
anneals silicon of the source/drain with the silicidable metal layer to form a metal silicide source/drain contact,
anneals polysilicon of the gate with the silicidable metal layer to form a metal silicide gate contact, and
anneals the material stack and the silicidable metal layer to form the metal silicide structure on the side of the isolation structure.

13 . The method of claim 9 , wherein:
the second deposition process deposits the silicidable metal layer on a gate and a source/drain on or in the semiconductor surface layer; and the annealing the material stack and the silicidable metal layer concurrently:
anneals silicon of the source/drain with the silicidable metal layer to form a metal silicide source/drain contact,
anneals polysilicon of the gate with the silicidable metal layer to form a metal silicide gate contact, and
anneals the silicon-rich dielectric layer, the oxynitride layer, the polysilicon layer, and the silicidable metal layer to form the metal silicide structure on the side of the isolation structure.

14 . The method of claim 9 , wherein the silicidable metal layer includes one of titanium, cobalt, tungsten, nickel-platinum, and nickel.

15 . The method of claim 9 , wherein: the silicon-rich dielectric layer is one of a silicon-rich nitride material, a silicon-rich carbon nitride material, and a silicon-rich oxynitride material having a silicon-to-nitrogen atomic ratio of approximately 1.5 to 10 as measured by an elemental analysis technique.

16 . The method of claim 9 , wherein the silicon-rich dielectric layer is a silicon-rich oxide material or a silicon-rich oxynitride material having a silicon-to-oxygen atomic ratio of approximately 1.0 to 10 as measured by an elemental analysis technique.

17 . The method of claim 9 , wherein the silicon-rich dielectric layer is a silicon-rich carbide material or a silicon-rich carbon nitride material having a silicon-to-carbon atomic ratio of approximately 1.5 to 10 as measured by an elemental analysis technique.

Assignees

• Texas Instruments Inc

Inventors

• Nandakumar Mahalingam
• Wang Yuguo
• Bu Haowen

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H10W20/498 Primary

  Resistive arrangements or effects of, or between, wiring layers · CPC title