Memory power control unit

Patent metadata

Field	Value
Publication number	US-12494248-B2
Application number	US-202318535443-A
Country	US
Kind code	B2
Filing date	Dec 11, 2023
Priority date	Dec 16, 2022
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A memory power control unit, MPCU, is provided for preventing unauthorised access to data stored in a volatile memory, the MPCU comprising a power controller comprising an input configured to receive a signal from a tamper detection circuit, a first supply input configured 5 to receive a first supply voltage, a first reference input configured to receive a first reference voltage, a supply output configured to output a supply voltage to the volatile memory, a reference output configured to output a reference voltage to the volatile memory, wherein, in response to receipt of a signal at the input indicative of an attempt to tamper with the volatile memory, the power controller is configured to output a reduced supply voltage via the supply 10 output for a first predetermined time period, wherein the reduced supply voltage is less than the first supply voltage.

First claim

We claim:

1 . A memory power control unit, MPCU, for preventing unauthorised access to data stored in a volatile memory, the MPCU comprising:
a power controller comprising:
an input configured to receive a signal from a tamper detection circuit;
a first supply input configured to receive a first supply voltage;
a first reference input configured to receive a first reference voltage;
a supply output configured to output a supply voltage to the volatile memory;
a reference output configured to output a reference voltage to the volatile memory;
wherein, in response to receipt of a signal at the input indicative of an attempt to tamper with the volatile memory, the power controller is configured to output a reduced supply voltage via the supply output for a first predetermined time period, wherein the reduced supply voltage is less than the first supply voltage, wherein the power controller comprises a switching device, wherein the switching device is configured to selectively connect the supply output to either the first supply input or a second supply input, wherein the second supply input is configured to receive the reduced supply voltage.

2 . The memory power control unit of claim 1 , further comprising;
a timer circuit, wherein the timer circuit is configured to set the first predetermined time period.

3 . The memory power control unit of claim 2 , wherein:
the timer circuit comprises a capacitor; and the power controller comprises a logic circuit; wherein, in response to receipt of a signal indicative of an attempt to tamper with the volatile memory:
the timer circuit is configured to output a discharge voltage from the capacitor; and
the logic circuit is configured to compare the discharge voltage to a predetermined threshold, wherein the logic circuit is configured to provide the reduced supply voltage to the supply output until the discharge voltage reaches the predetermined threshold.

4 . The memory power control unit of claim 2 , wherein the timer circuit comprises:
a first input configured to receive a signal from the tamper detection circuit; a second input configured to receive a charging voltage; a transistor coupled to both the first input and the second input, wherein the capacitor is coupled to an output of the transistor; and an output; wherein, in response to receipt of a signal at the first input indicative of an attempt to tamper with the volatile memory, the transistor is configured to charge and then discharge the capacitor to provide the discharge voltage to the output.

5 . The memory power control unit of claim 1 , wherein, in response to receipt of a signal at the input indicative of an attempt to tamper with the volatile memory, the power controller is configured to output an increased reference voltage via the reference output for a second predetermined time period, wherein the increased reference voltage is higher than the first reference voltage but less than or equal to the first supply voltage.

6 . The memory power control unit of claim 5 , wherein the first predetermined time period is greater than or equal to the second predetermined time period.

7 . The memory power control unit of claim 5 , further comprising;
a timer circuit, wherein the timer circuit is configured to set the first predetermined time period and the second predetermined time period.

8 . The memory power control unit of claim 7 , wherein:
the timer circuit comprises a capacitor; and the power controller comprises a logic circuit; wherein, in response to receipt of a signal indicative of an attempt to tamper with the volatile memory:
the timer circuit is configured to output a discharge voltage from the capacitor; and
the logic circuit is configured to:
compare the discharge voltage to a first predetermined threshold, wherein the logic circuit is configured to provide the reduced supply voltage to the supply output until the discharge voltage reaches the first predetermined threshold; and
compare the discharge voltage to a second predetermined threshold, wherein the logic circuit is configured to provide the increased reference voltage to the reference output until the discharge voltage reaches the second predetermined limit, wherein the second predetermined threshold is greater than or equal to the first predetermined threshold.

9 . The memory power control unit of claim 8 , wherein the logic circuit comprises at least one switching device, wherein the at least one switching device is configured to selectively connect:
the supply output to either the first supply input or a second supply input, wherein the second supply input is configured to receive the reduced supply voltage; and the reference output to either the first reference input or a second reference input, wherein the second reference input is configured to receive the increased reference voltage.

10 . The memory power control unit of claim 5 , further comprising:
a first timer circuit configured to set the first predetermined time period; and a second timer circuit configured to set the second predetermined time period.

11 . The memory power control unit of claim 10 , wherein:
the power controller comprises a first logic circuit coupled to the first timer circuit, and a second logic circuit coupled to the second timer circuit; and each timer circuit comprises a respective capacitor; wherein, in response to receipt of a signal indicative of an attempt to tamper with the volatile memory:
each timer circuit is configured to output a discharge voltage from the respective capacitor; and
the respective logic circuit is configured to receive the discharge voltage from the respective timer circuit; and
until the discharge voltage from the first timer circuit reaches a first predetermined threshold, the first logic circuit is configured to provide the reduced supply voltage to the supply output; and
until the discharge voltage from the second timer circuit reaches a second predetermined threshold, the second logic circuit is configured to provide the increased reference voltage to the reference output.

12 . The memory power control unit of claim 11 , wherein:
the first logic circuit comprises a first switching device, the first switching device configured to selectively connect the supply output to either the first supply input or a second supply input, wherein the second supply input is configured to receive the reduced supply voltage; and the second logic circuit comprises a second switching device, the second switching device configured to selectively connect the reference output to either the first reference input or a second reference input, wherein the second reference input is configured to receive the increased reference voltage.

13 . The memory power control unit of claim 11 , wherein each timer circuit comprises:
a first input configured to receive a signal from the tamper detection circuit; a second input configured to receive a charging voltage; a transistor coupled to both the first input and the second input, wherein the capacitor is coupled to an output of the transistor; and an output; wherein, in response to receipt of a signal at the first input indicative of an attempt to tamper with the volatile memory, the transistor is configured to charge and then discharge the capacitor to provide the discharge voltage to the output.

14 . The memory power control unit of claim 13 , wherein each timer circuit further comprises:
a resistor coupled between the output of the transistor and ground, wherein the resistor is configured to ensure that the capacitor remains in an uncharged

Assignees

• Nxp Bv

Inventors

• Ghosh Prokash
• Ghosh Jyotirmoy
• Abeln Glenn Charles
• Prasad Dwarka
• Kohli Rajat
• Singh Jainendra
• Mishra Jwalant Kumar

Classifications

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G06F21/81

  by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations · CPC title

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F21/75

  by inhibiting the analysis of circuitry or operation · CPC title