Apparatuses and systems for increasing a speed of removal of data stored in a memory cell

Patent metadata

Field	Value
Publication number	US-2016379705-A1
Application number	US-201514748009-A
Country	US
Kind code	A1
Filing date	Jun 23, 2015
Priority date	Jun 23, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

Embodiments include apparatuses, methods, and systems including a circuit which may increase a speed of removal of data stored in a memory cell. In embodiments, the circuit may include a control logic to detect a signal and a boost circuit coupled to the control logic to allow the control logic to disable an operation of the boost circuit in response to detection of the signal. A discharge device may be coupled to the boost circuit to accelerate leakage of a leakage current in response to the detection of the signal. In the embodiment, the leakage current is a leakage current of a memory cell coupled to the discharge device and acceleration of the leakage of the leakage current and the disablement of the operation of the boost circuit may increase a speed of erasure of data in the memory cell. Other embodiments may also be described and claimed.

First claim

1 . A circuit, comprising:
a control logic including a detection logic to detect a signal; a boost circuit coupled to the control logic to allow the control logic to disable an operation of the boost circuit in response to a detection of the signal; and a discharge device coupled to an output terminal of the boost circuit to accelerate a leakage of a leakage current in response to the detection of the signal, wherein the leakage current is a leakage current associated with an access transistor of a memory cell coupled to the discharge device, and wherein an acceleration of the leakage of the leakage current and a disablement of the operation of the boost circuit increases a speed of erasure of data in the memory cell.

2 . The circuit of claim 1 , wherein the access transistor comprises an access transistor of a dynamic random access memory (DRAM) cell.

3 . The circuit of claim 1 wherein the control logic, boost circuit, and discharge device comprise parts of a charge pump circuit and the discharge device comprises a transistor

4 . The circuit of claim 1 , wherein the signal is a control signal received in response to a DRAM power-off signal.

5 . The circuit of claim 1 , wherein the signal comprises an attack signal issued in response to a cold-boot attack.

6 . The circuit of claim 1 , wherein in response to the detection of the signal, the discharge device is controllable to short an output signal of the boost circuit from a negative voltage to ground.

7 . The circuit of claim 1 , further including a ring oscillator coupled to the boost circuit, wherein in response to the detection of the signal, the control logic is controllable to disable the ring oscillator.

8 . The circuit of claim 1 , wherein the signal comprises a signal indicating a power down of a memory chip including the memory cell.

9 . The circuit of claim 1 , wherein the discharge device comprises a first discharge device, the circuit further comprising a voltage generator including a second discharge device coupled to a storage node of the memory cell.

10 - 15 . (canceled)

16 . A system, comprising:
a memory array; and a charge pump circuit coupled to a word line corresponding to a plurality of memory cells in the memory array, the charge pump circuit comprising:
a control logic including a detection logic to detect a signal, the control logic coupled to disable an operation of the charge pump circuit in response to a detection of the signal by the detection logic; and
a discharge device coupled to an output terminal of the charge pump circuit to accelerate leakage of a leakage current associated with a memory cell of the plurality of memory cells in response to the detection of the signal, wherein a disablement of the operation of the charge pump circuit and an acceleration of a leakage of the leakage current are to speed up erasure of the memory cell.

17 . The system of claim 16 , wherein the memory array is a dynamic random access memory (DRAM) array.

18 . The system of claim 16 , wherein the charge pump circuit comprises a first charge pump device, the system further comprising a second charge pump device, wherein the second charge pump device is coupled to a transistor back-gate node of an access transistor associated with the memory cell.

19 . The system of claim 18 , wherein the discharge device comprises a first discharge device, the system further comprising a second discharge device coupled to the second charge pump device, wherein an activation of the second discharge device is controllable to accelerate a current leakage at the access transistor of the memory cell.

20 . The system of claim 16 , further comprising a voltage generator coupled to the memory cell.

21 . The system of claim 16 , wherein the signal is a control signal which signals one or more of a sleep mode, hibernation mode, hybrid mode, power-off, and shut-down of a computing device including the memory array.

22 . The system of claim 16 , wherein the leakage current is a sub-threshold leakage current of an access transistor of the memory cell.

23 . A circuit, comprising:
means for disabling an operation in response to a detected signal; and means for accelerating a leakage of a leakage current in response to the detected signal, wherein the leakage current is a leakage current associated with an access transistor of the memory cell and wherein accelerating of the leakage of the leakage current and a disabling of the operation by the means for disabling increases a speed of erasure of data in a memory cell.

24 . The circuit of claim 23 , wherein the means for disabling the operation comprises means for disabling a ring oscillator.

25 . The circuit of claim 23 , wherein the means for accelerating the leakage of the leakage current comprises means to short an output signal of a boost circuit from a negative voltage to ground.

Assignees

• Intel Corp

Inventors

• Lu Shih-Lien
• Naeimi Helia
• Tomishima Shigeki

Classifications

• G11C11/4072 Primary

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4096 Primary

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4094 Primary

  Bit-line management or control circuits · CPC title

• G11C11/4078

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title