Memory cell with de-initialization circuitry

Patent metadata

Field	Value
Publication number	US-9608827-B1
Application number	US-201614997937-A
Country	US
Kind code	B1
Filing date	Jan 18, 2016
Priority date	Jan 18, 2016
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Circuits and approaches for de-initializing memory circuits. In one implementation, a memory circuit includes a plurality of memory cells. Each memory cell includes a pair of cross-coupled inverters and first and second access transistors coupled to the pair of cross-coupled inverters. A first bit line is coupled to the first access transistor, and a second bit line is coupled to the second access transistor. A de-initialization circuit is coupled to the first and second bit lines. The de-initialization circuit is configured and arranged to equalize signal states on the first and second bit lines in response to a de-initialization signal.

First claim

What is claimed is:

1. A memory circuit, comprising:
a plurality of memory cells, each memory cell including:
a pair of cross-coupled inverters;
a first access transistor coupled to the pair of cross-coupled inverters; and
a second access transistor coupled to the pair of cross-coupled inverters;

a first bit line coupled to the first access transistor;
a second bit line coupled to the second access transistor;
a de-initialization circuit coupled to the first and second bit lines, wherein the de-initialization circuit is configured and arranged to equalize signal states on the first and second bit lines in response to a first state of a de-initialization signal; and
a control circuit coupled to the de-initialization circuit, wherein the control circuit is configured and arranged to:
enable power to the plurality of memory cells,
disable power to the plurality of memory cells after the enabling of power to the plurality of memory cells,
assert the de-initialization signal to the first state while power is disabled to the plurality of memory cells,
de-assert the de-initialization signal to a second state after the equalizing and while power is disabled to the plurality of memory cells.

2. The memory circuit of claim 1 , wherein the de-initialization circuit includes a transistor coupled between the first and second bit lines and the transistor is arranged to short-circuit the first and second bit lines in response to the de-initialization signal.

3. The memory circuit of claim 1 , wherein in each memory cell:
the first bit line of the memory cell is coupled to a write-bit node; and
the de-initialization circuit includes a logic circuit arranged to drive the signal state on the second bit line to a signal state equivalent to the signal state of the write-bit node in response to a first state of the de-initialization signal and to drive the signal state on the second bit line to a signal state opposite the signal state of the write-bit node in response to a second state of the de-initialization signal.

4. The memory circuit of claim 1 , wherein:
the plurality of memory cells are arranged in columns and rows;
the memory circuit further includes a plurality of address lines, wherein each respective address line of the plurality of address lines is coupled to the first and second access transistors of the memory cells in one of the rows; and
the de-initialization circuit is further configured and arranged to simultaneously enable the first and second access transistors coupled to the plurality of address lines in response to the de-initialization signal.

5. A circuit arrangement, comprising:
an SRAM circuit arrangement including a plurality of memory cells, each memory cell including:
a pair of cross-coupled inverters;
a first access transistor coupled to the pair of cross-coupled inverters; and
a second access transistor coupled to the pair of cross-coupled inverters;

a first bit line coupled to the first access transistor;
a second bit line coupled to the second access transistor;
a de-initialization circuit coupled to the first and second bit lines, wherein the de-initialization circuit is configured and arranged to equalize signal states on the first and second bit lines in response to a first state of a de-initialization signal; and
a physically unclonable function (PUF) control circuit coupled to the SRAM circuit arrangement, wherein the PUF control circuit is configured and arranged to:
enable power to the plurality of memory cells,
disable power to the plurality of memory cells after the enabling of power to the plurality of memory cells,
assert the de-initialization signal to the first state while power is disabled to the plurality of memory cells,
de-assert the de-initialization signal to a second state after the equalizing and while power is disabled to the plurality of memory cells,
enable power to the plurality of memory cells after the de-assertion of the de-initialization signal,
read a PUF value from the SRAM circuit arrangement after enabling power after the de-asserting the de-initialization signal to the second state, and
output the PUF value.

6. The circuit arrangement of claim 5 , wherein the de-initialization circuit includes a transistor coupled between the first and second bit lines and the transistor is arranged to short-circuit the first and second bit lines in response to the de-initialization signal.

7. The circuit arrangement of claim 5 , wherein in each memory cell:
the first bit line of the memory cell is coupled to a write-bit node; and
the de-initialization circuit includes a logic circuit arranged to drive the signal state on the second bit line to a signal state equivalent to the signal state of the write-bit node in response to a first state of the de-initialization signal and to drive the signal state on the second bit line to a signal state opposite the signal state of the write-bit node in response to a second state of the de-initialization signal.

8. The circuit arrangement of claim 5 , wherein:
the plurality of memory cells are arranged in columns and rows;
the SRAM circuit arrangement further includes a plurality of address lines, wherein each respective address line of the plurality of address lines is coupled to the first and second access transistors of the memory cells in one of the rows; and
the de-initialization circuit is further configured and arranged to simultaneously enable the first and second access transistors coupled to the plurality of address lines in response to the de-initialization signal.

9. The circuit arrangement of claim 5 , further comprising:
a plurality of configurable logic blocks coupled to the SRAM circuit arrangement; and
a plurality of programmable interconnect elements coupled to the SRAM circuit arrangement.

10. The circuit arrangement of claim 9 , wherein the PUF control circuit is implemented in the plurality of configurable logic blocks and the plurality of programmable interconnect elements.

11. A method of de-initializing an SRAM, the SRAM including rows and columns of memory cells and respective pairs of first and second bit lines coupled to the columns of memory cells, comprising:
enabling power to the rows and columns of memory cells in the SRAM;
disabling power to the rows and columns of memory cells after the enabling of power to the rows and columns of memory cells;
asserting a de-initialization signal to a first state while power is disabled to the rows and columns of memory cells;
equalizing signal states on each pair of first and second bit lines in response to the first state of the de-initialization signal and while power is disabled to the rows and columns of memory cells; and
de-asserting the de-initialization signal to a second state after the equalizing.

12. The method of claim 11 , wherein the equalizing includes short-circuiting each pair of first and second bit lines.

13. The method of claim 11 , wherein the equalizing includes driving each pair of first and second bit lines to a value on a write-bit node.

14. The method of claim 11 , further comprising simultaneously addressing the rows of memory cells in response to the de-initialization signal.

15. The method of claim 11 , further comprising addressing each row of the rows of memory cells one at a time.

16. The method of claim 11 , further comprising:
enabling power to the plurality of memory cells after de-asserting the de-initialization signal;
reading a PUF value from the SRAM after enabling power after de-asserting the de-initialization signal; and
outputting the PUF value.

Assignees

• Xilinx Inc

Inventors

• Trimberger Stephen M

Classifications

• H04L9/3278 Primary

  using physically unclonable functions [PUF] · CPC title

• G06F21/44

  Program or device authentication · CPC title

• G06F21/73

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C11/41

  forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger · CPC title