Memory device and refresh method thereof

Patent metadata

Field	Value
Publication number	US-12494244-B2
Application number	US-202218076932-A
Country	US
Kind code	B2
Filing date	Dec 7, 2022
Priority date	Jul 22, 2022
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A memory device is provided. The memory device includes: a first memory cell array including a first row and a second row; and a self-refresh circuit configured to control refresh in response to a first self-refresh entry signal, and stop refresh of the second row after refreshing the first row in response to a self-refresh exit signal.

First claim

What is claimed is:

1 . A memory device comprising:
a first memory cell array comprising a plurality of rows, the plurality of rows comprising a first row and a second row; and a self-refresh circuit configured to control refresh in response to a first self-refresh entry signal, and stop refresh of the second row after refreshing the first row in response to a self-refresh exit signal, wherein the self-refresh circuit is configured to output a refresh row address in a first period of a self-refresh control signal and output a row hammer address in a second period of the self-refresh control signal, and wherein the self-refresh control signal is maintained at an enable level for a period comprising the first period and the second period.

2 . The memory device of claim 1 , wherein the first row is a row determined to be refreshed at a time point at which the self-refresh exit signal is received.

3 . The memory device of claim 1 , wherein the self-refresh circuit comprises:
a signal generator configured to output the self-refresh control signal in response to the first self-refresh entry signal; and a refresh counter configured to output the refresh row address indicating a row to be refreshed during an enable level period of the self-refresh control signal.

4 . The memory device of claim 3 , wherein the signal generator is further configured to output a counter control signal to the refresh counter based on the self-refresh control signal being at an enable level for a predetermined period, and
wherein the refresh counter is further configured to increment the refresh row address in response to the counter control signal.

5 . The memory device of claim 3 , wherein, based on the self-refresh control signal being at an enable level for a predetermined period, the refresh row address indicates a predetermined number of rows.

6 . The memory device of claim 5 , wherein the refresh counter comprises:
a main counter configured to increment first bits in a first area of the refresh row address in response to a counter control signal; and a sub-counter configured to increment r bits in a second area of the refresh row address in response to a sub-counter control signal, wherein the second area is configured of r bits, wherein the first area is configured of 2 r bits, and wherein the sub-counter control signal is inputted 2 r times.

7 . The memory device of claim 5 , wherein the refresh counter is configured to output the refresh row address to sequentially refresh the predetermined number of rows based on the self-refresh control signal being at an enable level for the predetermined period.

8 . The memory device of claim 5 , wherein the refresh counter is configured to output the refresh row address to simultaneously refresh the predetermined number of rows based on the self-refresh control signal being at an enable level for the predetermined period.

9 . The memory device of claim 3 ,
wherein the row hammer address is an address of a row adjacent to a row having a largest number of accesses.

10 . The memory device of claim 9 , wherein the self-refresh circuit is configured to reset a number of accesses of the row having the largest number of accesses, after outputting the row hammer address.

11 . The memory device of claim 9 , wherein the first period temporally precedes the second period.

12 . The memory device of claim 9 , wherein the second period temporally precedes the first period.

13 . The memory device of claim 1 , further comprising a second memory cell array,
wherein the self-refresh circuit comprises: a signal generator configured to output a the self-refresh control signal comprising a first enable level period and a second enable level period in response to the first self-refresh entry signal; a first refresh counter configured to output a first refresh row address indicating a row to be refreshed in the first memory cell array in the first enable level period; and a second refresh counter configured to output a second refresh row address indicating a row to be refreshed in the second memory cell array in the second enable level period.

14 . The memory device of claim 1 , further comprising a second memory cell array, a third memory cell array, and a fourth memory cell array,
wherein the self-refresh circuit comprises: a signal generator configured to output the self-refresh control signal comprising a first enable level period and a second enable level period in response to the first self-refresh entry signal; a first refresh counter configured to output a first refresh row address indicating a row to be refreshed in the first memory cell array and a row to be refreshed in the second memory cell array in the first enable level period; and a second refresh counter configured to output a second refresh row address indicating a row to be refreshed in the third memory cell array and a row to be refreshed in the fourth memory cell array in the second enable level period.

15 . The memory device of claim 1 , wherein the self-refresh circuit is configured to control the refresh to be refreshed from the first row in response to a second self-refresh entry signal received after the self-refresh exit signal.

16 . The memory device of claim 1 , wherein the self-refresh circuit is configured to control the refresh to be refreshed from the second row in response to a second self-refresh entry signal received after the self-refresh exit signal.

17 . A memory device comprising:
a command decode circuit configured to decode a command, and output a self-refresh entry signal and a self-refresh exit signal; a self-refresh circuit configured to output a self-refresh control signal and a refresh row address in response to the self-refresh entry signal, and stop output of the self-refresh control signal and the refresh row address in response to the self-refresh exit signal; and a row address multiplexer configured to output the refresh row address in response to a high level of the self-refresh control signal, and output an operation row address in response to a low level of the self-refresh control signal, wherein the self-refresh circuit is configured to output the refresh row address as the refresh row address in a first period of the self-refresh control signal and output a row hammer address as the refresh row address in a second period of the self-refresh control signal, wherein the self-refresh control signal is maintained at an enable level for a period comprising the first period and the second period, wherein the refresh row address indicates a row to be refreshed, and wherein the operation row address indicates a row to be written to, read from, or erased.

18 . The memory device of claim 17 , wherein the self-refresh circuit is configured to increment the refresh row address based on the self-refresh control signal being at a high level for a predetermined period.

19 . The memory device of claim 17 ,
wherein the row hammer address indicates a row adjacent to a row having a largest number of accesses.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Jongpil

Classifications

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C2211/4067

  Refresh in standby or low power modes · CPC title