Memory device for refresh and memory system including the same

Patent metadata

Field	Value
Publication number	US-10115448-B2
Application number	US-201615194784-A
Country	US
Kind code	B2
Filing date	Jun 28, 2016
Priority date	Oct 20, 2015
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.

First claim

What is claimed is:

1. A memory device comprising:
a memory bank including a plurality of memory blocks, each memory block including a plurality of memory cells arranged in rows and columns;
a row selection circuit configured to select one or more rows such that the memory device performs an access operation and a refresh operation with respect to the memory bank in response to an active command received from a memory controller; and
a refresh controller configured to control the row selection circuit such that the memory device is operated selectively in an access mode in response to the active command or a self-refresh mode in response to a self-refresh command received from the memory controller, and the refresh controller configured to, when entering the self-refresh mode, control the row selection circuit such that the refresh operation is performed first by a burst number in response to a first clock signal having a first clock period, and then in response to a second clock signal having a second clock period longer than the first clock period,
wherein the refresh operation is performed in the access mode in response to the active command,
wherein the refresh operation is performed in the self-refresh mode in response to at least one clock signal, and
wherein the refresh controller includes:
a pull-in counter configured to store a count value changing between a minimum count value and a maximum count value such that the count value is increased whenever the refresh operation for one row of the memory bank is completed and the count value is decreased whenever an average refresh interval time elapses.

2. The memory device of claim 1 , further comprising:
a mode register configured to store burst information for controlling the memory device,
wherein the burst number is determined based on the burst information stored in the mode register and the burst information is provided through a mode register write command received from the memory controller.

3. The memory device of claim 1 , wherein the burst number is determined based on a time point when the count value of the pull-in counter attains the maximum count value.

4. The memory device of claim 1 , wherein the refresh controller is configured to, when the count value of the pull-in counter corresponds to the maximum count value, control the row selection circuit such that the refresh operation of the memory bank is not performed even though the active command is received.

5. The memory device of claim 1 , wherein the memory controller is configured to generate the self-refresh command based on a frequency of generating the active command.

6. The memory device of claim 1 , wherein the refresh controller is configured to generate an attention signal that is activated when a refresh operation is required with respect to the memory bank, and
wherein the memory controller is configured to generate the self-refresh command based on the attention signal.

7. The memory device of claim 1 , wherein the row selection circuit is configured to, in the access mode, enable a first memory block corresponding to an access address among the plurality of memory blocks and selectively enable or disable a second memory block corresponding to a refresh address among the plurality of memory blocks, and
wherein the row selection circuit is configured, in the self-refresh mode, to enable the second memory block corresponding to the refresh address.

8. The memory device of claim 1 , wherein the memory device is a three-dimensional memory device where a plurality of semiconductor dies are stacked vertically.

9. A memory system comprising:
a memory device; and
a memory controller configured to control the memory device,
wherein the memory device comprises:
a plurality of memory banks, each memory bank including a plurality of memory blocks;
a plurality of bank row selection circuits configured to perform an access operation and a refresh operation with respect to the plurality of memory banks; and
a refresh controller configured to control the plurality of bank row selection circuits such that the memory device is operated selectively in an access mode in response to an active command received from the memory controller or a self-refresh mode in response to a self-refresh command received from the memory controller, and the refresh controller configured to, when entering the self-refresh mode, control the row selection circuit such that the refresh operation is performed first by a burst number in response to a first clock signal having a first clock period, and then in response to a second clock signal having a second clock period longer than the first clock period,
wherein the refresh operation is performed in the access mode in response to the active command and the refresh operation is performed in the self-refresh mode in response to at least one clock signal, and
wherein the refresh controller includes:
a pull-in counter configured to store a count value changing between a minimum count value and a maximum count value such that the count value is increased whenever the refresh operation for one row of the memory bank is completed and the count value is decreased whenever an average refresh interval time elapses.

10. The memory system of claim 9 , wherein the refresh controller is configured to, when entering the self-refresh mode, control the plurality of bank row selection circuits such that the refresh operation is performed first by a burst number in response to a first clock signal having a first clock period, and then in response to a second clock signal having a second clock period longer than the first clock period.

11. The memory system of claim 9 , wherein the memory controller is configured to generate the self-refresh command based on a frequency of generating the active command and generate a self-refresh entry command when an idle state in which the access operation is not performed with respect all of the plurality of memory banks is maintained for a predetermined amount of time.

12. The memory system of claim 9 , wherein the refresh controller is configured to generate an attention signal that is activated when a refresh operation is required with respect to at least one of the plurality of memory banks, and
wherein the memory controller is configured to generate a refresh command based on the attention signal.

13. The memory system of claim 9 , wherein the memory device further comprises a mode register configured to store refresh bank information for controlling the memory device,
wherein the refresh bank information represents memory banks to be required the refresh operation among the plurality of memory banks, and
wherein the memory controller is configured to generate a mode register read command to receive the refresh bank information from the memory device and generate a refresh command based on the received refresh bank information.

14. A memory device comprising:
a memory cell array including a plurality of memory banks, each bank having a plurality of memory cells arranged in rows and columns;
a row decoder configured to select one or more rows for a refresh operation;
a refresh control circuit configured to control the row decoder such that the memory device performs the refresh operation, and the refresh controller configured to, when entering the self-refresh mode, control the row selection circuit such that the refresh operation is performed first by a burst number in response to a first clock signal having a first clock period, and then in response to a second clock signal having a second clock period longer than the first clock period; and
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Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jong-Ho
• Shin Seung-Jun
• Oh Tae-Young

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title