Mitigating voltage overshoot at a transmission line

Patent metadata

Field	Value
Publication number	US-12494232-B2
Application number	US-202217980828-A
Country	US
Kind code	B2
Filing date	Nov 4, 2022
Priority date	Nov 4, 2022
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

Methods, systems, and devices for voltage overshoot mitigation at a device are described. The device may include a first driver circuit configured to generate data symbols on a transmission line and may include a second driver circuit configured to pre-emphasize the data symbols on the transmission line. The device may include a first inductor and a second inductor in series with the transmission line. A conductive line may couple the second driver circuit with a node, of the transmission line, that is between the first inductor and the second inductor.

First claim

What is claimed is:

1 . A transmitter, comprising:
a first driver circuit configured to generate data symbols on a transmission line; a first inductor and a second inductor in series with the transmission line; a second driver circuit coupled with a node of the transmission line that is between the first inductor and the second inductor and configured to pre-emphasize the data symbols on the transmission line by driving current to the node of the transmission line; a conductive line that couples the second driver circuit with the node, of the transmission line, that is between the first inductor and the second inductor, wherein the conductive line is configured to convey the current to the node; an electrostatic discharge (ESD) circuit coupled with the node and the second driver circuit and configured to mitigate electrostatic discharge and voltage overshoot on the transmission line during operation of the first driver circuit, the ESD circuit comprising a first terminal coupled with the node between the first inductor and the second inductor, and comprising a second terminal coupled with a ground reference that is isolated from the node, wherein the first inductor and the second inductor are in series between the first driver circuit and an output pin of the transmitter; and a control circuit coupled with the first driver circuit and coupled with the second driver circuit, wherein the control circuit is configured to activate the first driver circuit and the second driver circuit.

2 . The transmitter of claim 1 , wherein the second driver circuit is configured to pre-emphasize the data symbols by being configured to:
increase a voltage level of first data symbols of the data symbols, the first data symbols representative of a first logic value based at least in part on driving the current to the transmission line; and decreases a voltage level of second data symbols of the data symbols, the second data symbols that are representative of a second logic value based at least in part on driving the current to the transmission line.

3 . The transmitter of claim 1 , wherein the second driver circuit comprises:
a capacitor comprising a first terminal coupled with the node that is between the first inductor and the second inductor.

4 . The transmitter of claim 3 , wherein the second driver circuit comprises:
a first switching component coupled with a voltage supply; and a second switching component coupled with a ground reference, wherein a second terminal of the capacitor is coupled with a node between the first switching component and the second switching component.

5 . The transmitter of claim 1 , wherein the first driver circuit comprises:
a first switching component coupled with a voltage supply; and a second switching component coupled with a ground reference.

6 . The transmitter of claim 5 , wherein the first driver circuit comprises:
a first resistor between the first switching component and the first inductor; and a second resistor between the second switching component and the first inductor.

7 . The transmitter of claim 1 ,
wherein the second inductor is between the first inductor and the IO output pin.

8 . A transmitter, comprising:
a driver circuit configured to generate a first data symbol on a transmission line and a second data symbol on the transmission line, the first data symbol representative of a first logic value and the second data symbol representative of a second logic value; a pre-emphasis driver circuit configured to increase a voltage of the first data symbol and to decrease a voltage level of the second data symbol by driving current to the transmission line at a node between two inductors that are in series with the transmission line; a conductive line that couples a capacitor of the pre-emphasis driver circuit with the node between the two inductors that are in series with the transmission line and is configured to convey the current to the node; a control circuit coupled with the driver circuit and coupled with the pre-emphasis driver circuit, wherein the control circuit is configured to activate the driver circuit and the pre-emphasis driver circuit; and an electrostatic discharge (ESD) circuit coupled with the node and the pre-emphasis driver circuit and configured to mitigate electrostatic discharge and voltage overshoot on the transmission line during operation of the driver circuit, the ESD circuit comprising a first terminal coupled with the node between the two inductors, and comprising a second terminal coupled with a ground reference that is isolated from the node, wherein the two inductors are in between the driver circuit and an output pin of the transmitter.

9 . The transmitter of claim 8 , the control circuit further comprising:
a controller configured to activate the driver circuit and the pre-emphasis driver circuit at the same time.

10 . The transmitter of claim 8 , the control circuit further comprising:
a controller configured to activate the driver circuit before activating the pre-emphasis driver circuit.

11 . The transmitter of claim 8 , wherein the driver circuit comprises:
a first sub-circuit configured to generate the first data symbol; and a second sub-circuit configured to generate the second data symbol.

12 . The transmitter of claim 11 , wherein the pre-emphasis driver circuit comprises:
a first sub-circuit configured to increase the voltage of the first data symbol; and a second sub-circuit configured to decrease the voltage of the second data symbol.

13 . The transmitter of claim 8 , wherein the pre-emphasis driver circuit comprises:
a first switching component coupled with a voltage supply; a second switching component coupled with a ground reference; and the capacitor comprising a first terminal coupled with a node between the first switching component and the second switching component, and a second terminal coupled with the node between the two inductors.

14 . A transmitter, comprising:
a driver circuit coupled with a transmission line; a first inductor and a second inductor coupled in series with the transmission line, the first inductor comprising a first terminal coupled with the driver circuit and a second terminal coupled with a first terminal of the second inductor; a pre-emphasis driver circuit coupled with the second terminal of the first inductor and the first terminal of the second inductor via a conductive line coupled with the transmission line and configured to drive current to pre-emphasize data symbols on the transmission line; a control circuit coupled with the driver circuit and coupled with the pre-emphasis driver circuit, wherein the control circuit is configured to activate the driver circuit and the pre-emphasis driver circuit; and an electrostatic discharge (ESD) circuit coupled with the pre-emphasis driver circuit and a node between the first inductor and the second inductor and configured to mitigate electrostatic discharge and voltage overshoot on the transmission line during operation of the driver circuit, the ESD circuit comprising a first terminal coupled with the node between the first inductor and the second inductor, and comprising a second terminal coupled with a ground reference that is isolated from the node, wherein the first inductor and the second inductor are in between the driver circuit and an output pin of the transmitter.

15 . The transmitter of claim 14 , wherein the driver circuit comprises:
a first switching component coupled with the transmission line via a first resistor; and a second switching component coupled with the transmi

Assignees

• Micron Technology Inc

Inventors

• Brox Martin
• Bach Martin
• Hein Thomas

Classifications

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C7/02 Primary

  with means for avoiding parasitic signals · CPC title

• G11C7/1057 Primary

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title