Interleaved T-coil structure and a method of manufacturing the T-coil structure

Patent metadata

Field	Value
Publication number	US-9502168-B1
Application number	US-201314081970-A
Country	US
Kind code	B1
Filing date	Nov 15, 2013
Priority date	Nov 15, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

In one embodiment, an integrated circuit is described. The integrated circuit includes a substrate, a dielectric stack, a first inductor and a second inductor. The dielectric stack may be formed above the substrate and includes first and second layers. The first inductor may be formed in both the first and second layers. The second inductor may also be formed in the first and second layers with a substantial portion of the first inductor structure overlaps with the second inductor structure.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate;
a dielectric stack on top of the substrate, wherein the dielectric stack includes first and second layers;
a first inductor structure formed in the first and second layers; and
a second inductor structure formed in the first and second layers, wherein a substantial portion of the first inductor structure vertically overlaps with the second inductor structure, and wherein the first and second inductor structures are connected using only three vias.

2. The integrated circuit as defined in claim 1 , wherein the first inductor structure includes a first inductance and the second inductor structure includes a second inductance, the first and second inductance are different, and wherein the first and second inductor structures include a magnetic coupling factor derived from vertical and horizontal magnetic coupling.

3. The integrated circuit as defined in claim 1 , wherein the first inductor structure includes a first inductance and the second inductor structure includes a second inductance, wherein the first and second inductances are substantially identical, and wherein the first and second inductor structures includes a magnetic coupling factor derived from vertical and horizontal magnetic coupling.

4. The integrated circuit as defined in claim 1 , wherein the first and second inductor structures further comprise a bridge capacitor formed between the first and second inductor structures, and wherein the bridge capacitor includes a bridge capacitance value.

5. The integrated circuit as defined in claim 4 , wherein the first inductor structure has a first end that serves as a first port for a circuit, wherein the second inductor structure has a first end that serves as a second port for the circuit, wherein the first and second inductors each have a second end that serves as a third port for the circuit, and wherein the first, second and third ports have impedance values that are defined by inductance values of the first and second inductor structures, a magnetic coupling factor, and the bridge capacitance value.

6. The integrated circuit as defined in claim 1 , wherein a portion of the first inductor structure in the first layer is substantially parallel to a portion of the second inductor structure in the first layer, and wherein the portion of the first inductor structure in the first layer is substantially overlapping with another portion of the second inductor structure in the second layer.

7. The integrated circuit as defined in claim 6 , wherein the portion of the first inductor structure in the first layer and the another portion of the second inductor structure in the second layer are more than 25% overlapping.

8. The integrated circuit as defined in claim 6 , wherein the portion of the first inductor structure and the portion of the second inductor structure are arranged to form a helical shape.

9. The integrated circuit as defined in claim 6 , wherein the portions of the first and second inductor structures are arranged to form shapes selected from at least one of: a circular shape, a rectangular shape, an octagonal shape, and a hexagonal shape.

10. The integrated circuit as defined in claim 6 , wherein the first inductor structure is formed from a first conductive path having a first width, wherein the second inductor structure is formed from a second conductive path having a second width that is different than the first width.

11. An integrated circuit, comprising:
a first inductor structure formed in first and second interconnect layers, wherein the first inductor structure is formed from first conductive paths having a first width; and
a second inductor structure formed in the first and second interconnect layers, wherein the second inductor structure is formed from second conductive paths having a second width that is different than the first width, wherein only first inductor structure surrounds the second inductor structure in the first interconnect layer, and wherein only the second inductor structure surrounds the first inductor structure in the second interconnect layer.

12. The integrated circuit as defined in claim 11 , wherein the first and second inductor structures overlap more than 50 percent.

13. The integrated circuit as defined in claim 11 , wherein a portion of the first inductor structure that is in the first interconnect layer is substantially parallel to a portion of the second inductor structure in the first interconnect layer and another portion of the second inductor structure in the second interconnect layer.

14. The integrated circuit as defined in claim 11 , wherein the first inductor structure is coupled in series with the second inductor structure.

15. A method of manufacturing a circuit structure, comprising:
forming a portion of a first inductor structure in a first interconnect layer;
forming a portion of a second inductor structure that is parallel with the first inductor structure in the first interconnect layer;
forming another portion of the second inductor structure in a second interconnect layer, wherein the portion of the first inductor structure substantially overlaps with the portion of the second inductor structure in the first interconnect layer and with the another portion of the second inductor structure in the second interconnect layer; and
forming another portion of the first inductor structure in the second interconnect layer, wherein the another portion of the first inductor structure substantially overlaps with the portion of the second inductor structure in the first interconnect layer and with the another portion of the second inductor structure in the second interconnect layer, wherein only the first inductor structure surrounds the second inductor structure in the first interconnect layer, and wherein only the second inductor structure surrounds the first inductor structure in the second interconnect layer.

16. The method as defined in claim 15 , wherein the portion of the first inductor structure overlaps more than 25 percent with the portion of the second inductor structure in the first interconnect layer and with the another portion of the second inductor structure in the second interconnect layer.

17. The method as defined in claim 15 , wherein the first and second inductor structures each include first and second ends, the method further comprising:
coupling a first port of the circuit structure to the first end of the first inductor structure;
coupling a second port of the circuit structure to the first end of the second inductor structure; and
coupling a third port of the circuit structure to the second ends of the first and second inductor structures.

18. The method as defined in claim 15 , wherein the first and second inductor structures are arranged to form shapes selected from at least one of: a circular shape, a rectangular shape, an octagonal shape, and a hexagonal shape.

Assignees

• Altera Corp

Inventors

• Ler Chun Lee
• Chen Shuxian

Classifications

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W44/00

  Electrical arrangements for controlling or matching impedance · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H01F27/2804 Primary

  Printed windings · CPC title

• H01F41/041

  Printed circuit coils (apparatus or processes for manufacturing printed circuits in general H05K3/00) · CPC title