Switching Converter with an Adjustable Transistor Component

Patent metadata

Field	Value
Publication number	US-2016006353-A1
Application number	US-201514853379-A
Country	US
Kind code	A1
Filing date	Sep 14, 2015
Priority date	May 31, 2011
Publication date	Jan 7, 2016
Grant date	—

Abstract

A switching converter includes a transistor arrangement having a plurality of n transistors, with n≧2, each including a gate terminal, and a load path between a source and a drain terminal, and at least m, with m≦n and m≧1 of the n transistors having a control terminal. The control terminal of each of the m transistors is configured to receive a control signal that adjusts an activation state of the transistor. The load paths of the plurality of n transistors are connected in parallel to form a load path of the transistor arrangement. A drive circuit is configured to adjust the activation state of the m transistors.

First claim

What is claimed is:

1 . A switching converter, comprising:
input terminals configured to apply an input voltage; output terminals configured to provide an output voltage; a rectifier-inductor arrangement coupled between the input terminals and the output terminals; a control circuit configured to receive an output voltage signal that is dependent on the output voltage, to provide a drive signal, and to assume one of at least two different operation modes; a transistor arrangement comprising a plurality of n transistors, with n≧2, each comprising a gate terminal, and a load path between a source and a drain terminal, and at least m, with m≦n and m≧1 of the n transistors comprising a control terminal wherein the control terminal of each of the m transistors is configured to receive a control signal that adjusts an activation state of the transistor, and wherein the load paths of the plurality of n transistors are connected in parallel forming a load path of the transistor arrangement; and a drive circuit configured to adjust the activation state of the m transistors comprising a control terminal independent of the others of the plurality of transistors to one of a first and second activation state, to determine a load condition of the transistor arrangement, and to select k, with k≧0, transistors that are driven to assume the first activation state and m−k transistors that are driven to assume the second activation state dependent on the operation mode of the control circuit.

2 . The switching converter of claim 1 , wherein one of the operation modes is a burst mode, and one of the operation modes is a normal operation mode.

3 . The switching converter of claim 2 , wherein each of the transistors has an active area, the individual transistors have identical sizes of their active area, and the drive circuit is configured to drive a first number of transistors to assume the first activation when the control circuit is in the normal operation mode, and to drive a second number of transistors to assume the first activation state when the control circuit is in the burst mode, wherein the second number is lower than the first number.

4 . The switching converter of claim 3 , wherein the first number equals the number n of transistors of the transistor arrangement.

5 . The switching converter of claim 3 , wherein the second number is between 0.1 times n and 0.6 times n.

6 . The switching converter of claim 1 , wherein each of the transistors has an active area, at least some of the n transistors have different sizes of their active areas, and the drive circuit is configured to select the k transistors that are in the first activation state such that a sum of the sizes of the active areas of the transistors in the first activation state is lower when the control circuit is in the burst mode than in the normal operation mode.

7 . The switching converter of claim 5 , wherein in the normal operation mode, the sum of the sizes of the active areas of the transistors in the first activation state equals an overall size of the active areas of the n transistors.

8 . The switching converter of claim 5 , wherein in the burst mode, the sum of the sizes of the active areas of the transistors in the first activation state is between 0.1 times n and 0.6 times equals an overall size of the active areas of the n transistors.

9 . The switching converter of claim 1 , wherein the rectifier arrangement has one of a buck topology, a boost topology, a buck-boost topology, a flyback topology.

Assignees

• Infineon Technologies Austria

Inventors

• Hirler Franz
• Feldtkeller Martin
• Deboy Gerald

Classifications

• H10D84/839

  comprising VDMOS · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D12/481 Primary

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03K17/04123

  in field-effect transistor switches · CPC title