High voltage polymer dielectric capacitor isolation device

Patent metadata

Field	Value
Publication number	US-9893008-B2
Application number	US-201615193355-A
Country	US
Kind code	B2
Filing date	Jun 27, 2016
Priority date	Aug 6, 2013
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

First claim

What is claimed is:

1. An isolation device, comprising:
a first copper layer disposed over a monolithic substrate;
a polymer dielectric layer disposed over the first copper layer, the polymer dielectric layer comprising primarily a layer of polyimide being at least 20 microns thick;
a second copper layer disposed over said polymer dielectric layer, said second copper layer extending into upper via holes in said polymer dielectric layer to form upper vias which make electrical connections to said first copper layer;
bondpads disposed on the second copper layer; and
a dielectric overcoat dielectric layer disposed over the second copper layer, said dielectric overcoat dielectric layer exposing the bondpads;
said isolation device containing a plurality of isolation components selected from the group consisting of a capacitor and a transformer, said isolation components being formed in at least said first copper layer and said second copper layer, wherein each of said isolation components is operable to 400 volts continuous operation, and able to withstand a voltage transient up to 5000 root-mean-square (rms) volts and a voltage surge up to 10000 volts.

2. The isolation device of claim 1 , wherein said substrate is single crystal silicon.

3. The isolation device of claim 1 , wherein said first copper layer is 4 to 6 microns thick and said second copper layer is 4 to 6 microns thick.

4. An isolation device, comprising:
a first copper layer disposed over a monolithic substrate;
a polymer dielectric layer disposed over the first copper layer, the polymer dielectric layer comprising primarily a layer of polyimide being at least 20 microns thick;
a second copper layer disposed over said polymer dielectric layer, said second copper layer extending into upper via holes in said polymer dielectric layer to form upper vias which make electrical connections to said first copper layer;
bondpads disposed on the second copper layer; and
a dielectric overcoat dielectric layer disposed over the second copper layer, said dielectric overcoat dielectric layer exposing the bondpads;
said isolation device containing a plurality of isolation components selected from the group consisting of a capacitor and a transformer, said isolation components being formed in at least said first copper layer and said second copper layer, wherein:
each instance of said isolation components is a capacitor;
a lower plate of said capacitor is provided in said first copper layer;
an upper plate of said capacitor is provided in said second copper layer;
said lower plate is electrically coupled to a first instance of said bondpads through an instance of said upper vias;
said upper plate is electrically coupled to a second instance of said bondpads.

5. The isolation device of claim 4 , wherein said dielectric layer is at least 5 microns thick.

6. The isolation device of claim 4 , wherein each of said isolation components is operable to 400 volts continuous operation, and able to withstand a voltage transient up to 5000 root-mean-square (rms) volts and a voltage surge up to 10000 volts.

7. The isolation device of claim 4 , wherein said substrate is single crystal silicon.

8. The isolation device of claim 4 , wherein said first copper layer is 4 to 6 microns thick and said second copper layer is 4 to 6 microns thick.

9. An isolation device, comprising:
a first copper layer disposed over a monolithic substrate;
a polymer dielectric layer disposed over the first copper layer, the polymer dielectric layer comprising primarily a layer of polyimide being at least 20 microns thick;
a second copper layer disposed over said polymer dielectric layer, said second copper layer extending into upper via holes in said polymer dielectric layer to form upper vias which make electrical connections to said first copper layer;
bondpads disposed on the second copper layer; and
a dielectric overcoat dielectric layer disposed over the second copper layer, said dielectric overcoat dielectric layer exposing the bondpads;
said isolation device containing a plurality of isolation components selected from the group consisting of a capacitor and a transformer, said isolation components being formed in at least said first copper layer and said second copper layer, wherein:
each instance of said isolation components is a transformer;
a lower winding of said transformer is provided in said first copper layer;
an upper winding of said transformer is provided in said second copper layer;
said lower winding is electrically coupled to a first two instances of said bondpads through instances of said upper vias;
said upper plate is electrically coupled to a second two instances of said bondpads.

10. The isolation device of claim 9 , wherein each of said isolation components is operable to 400 volts continuous operation, and able to withstand a voltage transient up to 5000 root-mean-square (rms) volts and a voltage surge up to 10000 volts.

11. The isolation device of claim 9 , wherein said substrate is single crystal silicon.

12. The isolation device of claim 9 , wherein said first copper layer is 4 to 6 microns thick and said second copper layer is 4 to 6 microns thick.

Assignees

• Texas Instruments Inc

Inventors

• Bonifield Thomas Dyer
• Williams Byron
• Jaganathan Shrinivasan
• Larkin David
• Saraiya Dhaval Atul

Classifications

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title