Synchronizing updates of page table status indicators and performing bulk operations

Patent metadata

Field	Value
Publication number	US-9836411-B2
Application number	US-201615196093-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	May 30, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory. Synchronization may be used to facilitate memory management operations, such as bulk operations used to change a large section of memory to read-only, operations to manage a free list of memory pages, and/or operations associated with terminating processes.

First claim

What is claimed is:

1. A computer program product for performing operations in a computing environment, said computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
initiating, by a processor of the computing environment, a synchronization operation to instruct one or more other processors of the computing environment to commit pending updates of one or more status indicators of one or more entries of an address translation structure located in memory;
receiving, by the processor, a completion indication by the one or more other processors indicating completion of the synchronization operation;
invalidating, by the processor, based on receipt of the completion indication from the one or more other processors, one or more selected entries of one or more local caches, the one or more selected entries having at least one status indicator that has been updated; and
based on receiving the completion indication, parallel to the invalidating, performing an operation using one or more entries of the address translation structure.

2. The computer program product of claim 1 , wherein the invalidating comprises exclusively invalidating the one or more selected entries.

3. The computer program product of claim 1 , wherein the performing the operation comprises providing a free list of a plurality of units of memory.

4. The computer program product of claim 1 , wherein the performing the operation comprises managing memory, based on a process terminating.

5. The computer program product of claim 1 , wherein the one or more status indicators comprise at least one of a change indicator that indicates whether a unit of memory associated with the change indicator has been updated or a reference indicator that indicates whether the unit of memory associated with the reference indicator has been accessed.

6. The computer program product of claim 5 , wherein the unit of memory comprises a page of memory, the address translation structure comprises a page table, and wherein the change indicator and the reference indicator are located in a page table entry corresponding to the page of memory.

7. The computer program product of claim 1 , wherein the initiating the synchronization operation comprises issuing a synchronization instruction, the synchronization instruction to send a synchronization request to the one or more other processors.

8. The computer program product of claim 1 , wherein the operation is a bulk operation to be performed on a plurality of units of memory.

9. A computer system for performing operations in a computing environment, said computer system comprising:
a memory; and
a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
initiating, by a processor of the computing environment, a synchronization operation to instruct one or more other processors of the computing environment to commit pending updates of one or more status indicators of one or more entries of an address translation structure located in memory;
receiving, by the processor, a completion indication by the one or more other processors indicating completion of the synchronization operation;
invalidating, by the processor, based on receipt of the completion indication from the one or more other processors, one or more selected entries of one or more local caches, the one or more selected entries having at least one status indicator that has been updated; and
based on receiving the completion indication, parallel to the invalidating, performing an operation using one or more entries of the address translation structure, wherein the method further comprises initiating another synchronization operation prior to the invalidating, and wherein the invalidating is performed based on receiving a completion indication for the other synchronization operation.

10. The computer system of claim 9 , wherein the performing the operation comprises providing a free list of a plurality of units of memory.

11. The computer system of claim 9 , wherein the performing the operation comprises managing memory, based on a process terminating.

12. The computer system of claim 9 , wherein the one or more status indicators comprise at least one of a change indicator that indicates whether a unit of memory associated with the change indicator has been updated or a reference indicator that indicates whether the unit of memory associated with the reference indicator has been accessed.

13. The computer system of claim 9 , wherein the invalidating comprises exclusively invalidating the one or more selected entries.

14. The computer system of claim 9 , wherein the operation is a bulk operation to be performed on a plurality of units of memory.

15. A computer-implemented method of performing operations in a computing environment, said computer-implemented method comprising:
initiating, by a processor of the computing environment, a synchronization operation to instruct one or more other processors of the computing environment to commit pending updates of one or more status indicators of one or more entries of an address translation structure located in memory;
receiving, by the processor, a completion indication by the one or more other processors indicating completion of the synchronization operation;
invalidating, by the processor, based on receipt of the completion indication from the one or more other processors, one or more selected entries of one or more local caches, the one or more selected entries having at least one status indicator that has been updated; and
based on receiving the completion indication, parallel to the invalidating, performing an operation using one or more entries of the address translation structure.

16. The computer-implemented method of claim 15 , wherein the performing the operation comprises providing a free list of a plurality of units of memory.

17. The computer-implemented method of claim 15 , wherein the performing the operation comprises managing memory, based on a process terminating.

18. The computer-implemented method of claim 15 , wherein the one or more status indicators comprise at least one of a change indicator that indicates whether a unit of memory associated with the change indicator has been updated or a reference indicator that indicates whether the unit of memory associated with the reference indicator has been accessed.

19. The computer-implemented method of claim 15 , wherein the initiating the synchronization operation comprises issuing a synchronization instruction, the synchronization instruction to send a synchronization request to the one or more other processors.

Assignees

• IBM

Inventors

• Gschwind Michael K

Classifications

• G06F2212/452

  Instruction code · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title