Substrate, method for forming the same, display device and for forming the same

Patent metadata

Field	Value
Publication number	US-12484348-B2
Application number	US-202117784437-A
Country	US
Kind code	B2
Filing date	Jul 6, 2021
Priority date	Aug 28, 2020
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A substrate includes a base substrate, at least two bonding pads are arranged on the base substrate, the base substrate and an electronic element are bonded to each other through the at least two bonding pads, at least two pins are arranged on the electronic element, a protective layer is arranged at a side of the bonding pads away from the base substrate, and an opening region is arranged in the protective layer at each bonding pad, to expose partial surface of the bonding pad. A bonding combination layer made of a low-melting-point alloy material is arranged in the opening region, and the low-melting-point alloy material is capable of being melted at a first predetermined temperature, to enable the bonding pads and the pins to be bonded to each other.

First claim

What is claimed is:

1 . A method for forming a substrate, wherein the substrate comprises a base substrate,
wherein at least two bonding pads are arranged on the base substrate, the base substrate and an electronic element are bonded to each other through the at least two bonding pads, at least two pins are arranged on the electronic element, a protective layer is arranged at a side of the bonding pads away from the base substrate, and an opening region is arranged in the protective layer at each bonding pad, to expose partial surface of the bonding pad; a bonding combination layer made of a low-melting-point alloy material is arranged in the opening region, and the low-melting-point alloy material is capable of being melted at a first predetermined temperature, to enable the bonding pads and the pins to be bonded to each other; and wherein the method comprises providing the base substrate; forming the at least two bonding pads on the base substrate; forming the protective layer at the side of the bonding pads away from the base substrate; patterning the protective layer to form the opening region at each bonding pad; directly forming a low-melting-point alloy layer made of the low-melting-point alloy material at a side of the protective layer away from the base substrate, wherein at least a portion of the low-melting-point alloy layer is located in the opening region and at least another portion covers the protective layer; and patterning the low-melting-point alloy layer to form the bonding combination layer in the opening region.

2 . The method according to claim 1 , wherein the forming the low-melting-point alloy layer made of the low-melting-point alloy material at the side of the protective layer away from the base substrate, comprises:
depositing and forming the low-melting-point alloy layer at the side of the protective layer away from the base substrate through magnetron sputtering.

3 . The method according to claim 1 , wherein the patterning the low-melting-point alloy layer to form the bonding combination layer in the opening region, comprises:
applying a photoresist onto the low-melting-point alloy layer; exposing the photoresist by using a mask to form a photoresist unreserved region and a photoresist reserved region; wherein the photoresist reserved region corresponds to a region where a pattern of the bonding combination layer is located, and the photoresist unreserved region corresponds to a region other than the pattern; performing a developing process, to fully remove the photoresist at the photoresist unreserved region, and maintain a thickness of the photoresist at the photoresist reserved region; wherein the low-melting-point alloy layer at the photoresist unreserved region is fully etched off through an etching process, to form the pattern of the bonding combination layer; and removing the remaining photoresist.

4 . A method for forming a display device, wherein the display device comprises the substrate and the electronic element according to claim 1 , and the method comprises:
obtaining the substrate transferring the electronic element onto the substrate, to enable the pins of the electronic element to be aligned with the bonding combination layer on the bonding pads of the substrate; and heating to a second predetermined temperature, to enable the low-melting-point alloy material of the bonding combination layer to be melted, and enable the bonding pads and the pins to be bonded to each other, wherein the second predetermined temperature is greater than or equal to the first predetermined temperature.

5 . The method according to claim 4 , wherein the second predetermined temperature is 10° C.-50° C. higher than the first predetermined temperature.

6 . The method according to claim 1 , wherein the following relationships are met among the low-melting-point alloy material, a material that the bonding pads are made of and a material that the pins are made of: the low-melting-point alloy material is melted to dissociate a metal ion at the first predetermined temperature, the metal ion reacts with the material that the bonding pads are made of, to form a first compound, and the metal ion reacts with the material that the pins are made of, to form a second compound.

7 . The method according to claim 1 , wherein the low-melting-point alloy material is formed by doping a low-melting-point metal having a melting point lower than a predetermined value with at least one of silver, copper, bismuth, zinc, indium, antimony or lead.

8 . The method according to claim 7 , wherein the low-melting-point metal comprises tin, and the low-melting-point alloy material comprises: at least one of a tin-silver alloy, a tin-silver-copper alloy, a tin-zinc alloy, a tin-zinc-bismuth alloy, a tin-bismuth alloy, a tin-bismuth-silver alloy, a tin-copper alloy, and a ternary alloy formed by doping a tin-copper alloy with nickel, gold or silver.

9 . The method according to claim 8 , wherein the bonding pads are made of at least one of gold, silver, copper or tin, and the pins are made of at least one of gold, silver, copper or tin.

10 . The method according to claim 1 , wherein the first predetermined temperature is less than or equal to 250° C.

11 . The method according to claim 1 , wherein the bonding combination layer has a thickness of 0.5 μm to 4 μm in a direction perpendicular to the base substrate.

12 . The method according to claim 1 , wherein an area of an orthogonal projection of the opening region onto the base substrate is less than an area of an orthogonal projection of each bonding pad onto the base substrate.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Wang Meili
• Qi Qi

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/04

  of leadframes · CPC title