Source or drain structures with relatively high germanium content

Patent metadata

Field	Value
Publication number	US-12484272-B2
Application number	US-201816022508-A
Country	US
Kind code	B2
Filing date	Jun 28, 2018
Priority date	Jun 28, 2018
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a relatively high germanium content are described. In an example, an integrated circuit structure includes a fin including a semiconductor material. A gate stack is over an upper fin portion of the fin. A first epitaxial source or drain structure is embedded in the fin at a first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at a second side of the gate stack. The first and second epitaxial source or drain structures include silicon and germanium and have a same or greater atomic concentration of germanium than the fin.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a first fin and a second fin each having a lower fin portion and an upper fin portion, the upper fin portion comprising silicon and germanium, and the lower fin portion comprising a portion of an underlying bulk single crystalline silicon substrate having a semiconductor composition different than the upper fin portion, wherein the upper fin portion is in contact with the underlying bulk single crystalline silicon substrate; a gate stack over the upper fin portion of the first fin and the second fin, the gate stack having a first side opposite a second side; a first epitaxial source or drain structure embedded in the first fin at the first side of the gate stack; a second epitaxial source or drain structure embedded in the second fin at the first side of the gate stack, the second epitaxial source or drain structure merged with the first epitaxial source or drain structure in a region over a trench isolation structure, the first and second epitaxial source or drain structures comprising a lower semiconductor layer and a capping semiconductor layer, the lower semiconductor layer having a bottommost surface below an uppermost surface of the trench isolation structure, the lower semiconductor layer comprising silicon and germanium and having a same or greater atomic concentration of germanium than the upper fin portion of the fin, the capping semiconductor layer having a greater atomic concentration of germanium than the lower semiconductor layer, and the capping semiconductor layer having a top surface above an uppermost surface of the lower semiconductor layer; and a conductive electrode on the top surface of the capping semiconductor layer of one of the first epitaxial source or drain structure or the second epitaxial source or drain structure, wherein the top surface of the capping semiconductor layer is vertically between the conductive electrode and the uppermost surface of the lower semiconductor layer, and wherein the conductive electrode is overlapping with the capping semiconductor layer along a vertical axis.

2 . The integrated circuit structure of claim 1 , wherein the upper fin portion of each of the first fin and the second fin has a total atomic concentration of germanium in the range of 10-50%, the lower semiconductor layer has a total atomic concentration of germanium in the range of 50-70%, and the capping semiconductor layer has a total atomic concentration of germanium in the range of 70-100%.

3 . The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are doped with boron atoms.

4 . The integrated circuit structure of claim 1 , further comprising:
first and second dielectric sidewall spacers along the first and second sides of the gate stack, respectively.

5 . The integrated circuit structure of claim 1 , wherein the conductive electrode is in a partial recess in the capping semiconductor layer.

6 . The integrated circuit structure of claim 1 , further comprising: a dielectric spacer along sidewalls of the conductive electrode.

7 . The integrated circuit structure of claim 6 , wherein the capping semiconductor layer is confined between the dielectric spacer.

8 . An integrated circuit structure, comprising:
a first fin and a second fin each having a lower fin portion and an upper fin portion, the upper fin portion having a channel region comprising silicon and germanium, and the lower fin portion including a portion of an underlying bulk single crystalline silicon substrate having a semiconductor composition different than the channel region of the fin, wherein the channel region of the fin is in contact with the underlying bulk single crystalline silicon substrate; a gate stack over the upper fin portion of the first fin and the second fin, the gate stack having a first side opposite a second side; a first epitaxial source or drain structure embedded in the first fin at the first side of the gate stack; a second epitaxial source or drain structure embedded in the second fin at the first side of the gate stack, the second epitaxial source or drain structure merged with the first epitaxial source or drain structure in a region over a trench isolation structure, the first and second epitaxial source or drain structures having a bottommost surface below an uppermost surface of the trench isolation structure, the first and second epitaxial source or drain structures comprising silicon and germanium and having a greater atomic concentration of germanium than the upper fin portion of the fin, and the first and second epitaxial source or drain structures comprising a capping semiconductor layer above a lower semiconductor layer, the capping semiconductor layer having a top surface above an uppermost surface of the lower semiconductor layer; and a conductive electrode on the top surface of the capping semiconductor layer of one of the first epitaxial source or drain structure or the second epitaxial source or drain structure, wherein the top surface of the capping semiconductor layer is vertically between the conductive electrode and the uppermost surface of the lower semiconductor layer, and wherein the conductive electrode is overlapping with the capping semiconductor layer along a vertical axis.

9 . The integrated circuit structure of claim 8 , wherein the upper fin portion of the each of the first fin and the second fin has a total atomic concentration of germanium in the range of 10-50%, and the first and second epitaxial source or drain structures have a total atomic concentration of germanium greater than 50%.

10 . The integrated circuit structure of claim 8 , wherein the first and second epitaxial source or drain structures are doped with boron atoms.

11 . The integrated circuit structure of claim 8 , further comprising:
first and second dielectric sidewall spacers along the first and second sides of the gate stack, respectively.

12 . The integrated circuit structure of claim 8 , wherein the first and second conductive electrode is in a partial recess in the first and second epitaxial source or drain structures, respectively.

13 . The integrated circuit structure of claim 8 , further comprising: a dielectric spacer along sidewalls of the conductive electrode.

14 . An integrated circuit structure, comprising:
a first fin and a second fin each having a lower fin portion and an upper fin portion, the upper fin portion comprising silicon and germanium, and the lower fin portion comprising a portion of an underlying bulk single crystalline silicon substrate having a semiconductor composition different than the upper fin portion, wherein the upper fin portion is in contact with the underlying bulk single crystalline silicon substrate; a gate stack over the upper fin portion of the first fin and the second fin, the gate stack having a first side opposite a second side; first and second dielectric sidewall spacers along the first and second sides of the gate stack, respectively; a first epitaxial source or drain structure embedded in the first fin at the first side of the gate stack; and a second epitaxial source or drain structure embedded in the second fin at the first side of the gate stack, the second epitaxial source or drain structure merged with the first epitaxial source or drain structure in a region over a trench isolation structure, the first and second epitaxial source or drain structures having a bottommost surface below an uppermost surface of the trench isolation structure, the first and second epitaxial source or drain structures comprising silicon and germa

Assignees

• Intel Corp

Inventors

• Bomberger Cory
• Murthy Anand
• Guha Biswajeet
• Bowonder Anupama
• Ghani Tahir

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D89/10

  Integrated device layouts · CPC title