Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9685439-B1
Application number	US-201615144395-A
Country	US
Kind code	B1
Filing date	May 2, 2016
Priority date	May 2, 2016
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, R a , of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a plurality of fins on a semiconductor substrate;
forming source/drain regions on said fins,
wherein the source/drain regions have an uneven surface with a mean surface roughness, R a , of about 10 nm to about 50 nm;
forming a smoothing layer on the source/drain regions filling the uneven surface;
forming an etch stop layer overlying the smoothing layer;
removing a portion of the etch stop layer to expose a portion of the smoothing layer;
removing the exposed smoothing layer; and
forming a contact layer on the source/drain regions.

2. The method according to claim 1 , wherein the smoothing layer comprises germanium.

3. The method according to claim 1 , wherein the source/drain regions comprise SiGe having a first germanium content.

4. The method according to claim 3 , further comprising forming a first intermediate layer comprising SiGe having a second germanium content between the source/drain regions and the smoothing layer, wherein the second germanium content is less than the first germanium content.

5. The method according to claim 3 , further comprising forming a second intermediate layer comprising SiGe having a third germanium content between the smoothing layer and the etch stop layer, wherein the third germanium content is less than the first germanium content.

6. The method according to claim 1 , wherein the smoothing layer is substantially completely removed by a wet cleaning operation.

7. The method according to claim 1 , wherein the contact layer is formed by depositing a metal on the source and drain regions and performing a silicidation reaction between the metal and the source/drain regions.

8. The method according to claim 1 , wherein the source/drain regions have a mean surface roughness, R a , of about 10 nm to about 15 nm.

9. The method according to claim 8 , further comprising forming a silicon layer overlying the smoothing layer.

10. A method for manufacturing a semiconductor device, comprising:
forming a plurality of fins on a semiconductor substrate;
forming source/drain regions on the fins,
forming a germanium layer on the source/drain regions filling the uneven surface;
forming a first intermediate layer on the germanium layer;
forming an etch stop layer on the intermediate layer;
forming an interlayer dielectric overlying the source/drain regions;
forming an opening in the interlayer dielectric over a portion of the source/drain regions;
removing a portion of the etch stop layer and the first intermediate layer in the opening exposing a portion of the germanium layer;
removing the exposed germanium layer by a wet clean operation; and
forming a contact layer on the source/drain regions,
wherein the source/drain regions have an uneven surface having a ratio of a width W between adjacent peak heights of the source/drain regions to a height H of the peak heights (W/H) ranging from 5 to 1.

11. The method according to claim 10 , wherein the wet clean operation comprises oxidizing the germanium layer and dissolving the oxidized germanium.

12. The method according to claim 10 , wherein the source/drain regions comprise SiGe having a first germanium content.

13. The method according to claim 12 , wherein the first intermediate layer comprises SiGe having a second germanium content less than the first germanium content.

14. The method according to claim 12 , further comprising forming a second intermediate layer comprising SiGe having a third germanium content between the source/drain regions and the smoothing layer, wherein the third germanium content is less than the first germanium content.

15. The method according to claim 10 , wherein the germanium layer is substantially completely removed by a wet cleaning operation.

16. The method according to claim 10 , wherein the forming a contact layer comprises:
depositing a metal layer on the source/drain regions; and
applying heat to the metal layer and source/drain regions to cause a silicidation reaction between metal layer and the source/drain regions.

17. The method according to claim 10 , wherein the ratio of the width W between adjacent peak heights of the source/drain regions to the height H of the peak heights (W/H) ranges from 3 to 2.

18. The method according to claim 17 , further comprising forming a silicon layer overlying the smoothing layer.

19. A method for manufacturing a semiconductor device, comprising:
forming a plurality of fins on a semiconductor substrate;
forming SiGe source/drain regions on the fins,
wherein the source/drain regions comprise SiGe having a first germanium content, and the source/drain regions have an uneven surface;
forming a conformal SiGe layer having a second germanium content on the source/drain regions,
wherein the second germanium content is less than the first germanium content;
forming a germanium layer on the conformal SiGe layer having a second germanium content, the germanium layer filling the uneven surface;
forming an SiGe layer having a third germanium content on the germanium layer,
wherein the third germanium content is less than the second germanium content;
forming an etch stop layer on the SiGe layer having the third germanium content;
forming an interlayer dielectric overlying the source/drain regions;
forming an opening in the interlayer dielectric over a portion of the source/drain regions;
removing a portion of the etch stop layer and the SiGe layer having the third germanium content in the opening exposing a portion of the germanium layer;
removing the exposed germanium layer; and
forming a contact layer on the source/drain regions.

20. The method according to claim 19 , wherein the exposed germanium layer is removed by a wet clean operation comprising oxidizing the germanium layer and dissolving the oxidized germanium.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chen-Ming
• Chen Liang-Yi
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10P70/20

  Cleaning during device manufacture · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L29/45

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L21/02057

  Electricity · mapped topic