Source switched split LNA

Patent metadata

Field	Value
Publication number	US-12483194-B2
Application number	US-202418653486-A
Country	US
Kind code	B2
Filing date	May 2, 2024
Priority date	Jul 15, 2016
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.

First claim

What is claimed is:

1 . An amplifier including:
(a) a plurality of independently-controlled low noise amplifiers (LNAs), each including at least an input transistor having a source terminal; and (b) a source switch coupled between the source terminal of the input transistor of a first of the independently-controlled LNAs and the source terminal of the input transistor of a second of the independently-controlled LNAs, the source switch configured to connect the source terminals while only one of the first and second independently-controlled LNAs is enabled, and disconnect the source terminals while both of the first and second independently-controlled LNAs are enabled.

2 . The amplifier of claim 1 , further including at least one gate capacitance module, each having a first terminal coupled to a gate of an associated input transistor of one of the independently-controlled LNAs, and a second terminal coupled to the source terminal of the associated input transistor.

3 . The amplifier of claim 2 , wherein each gate capacitance module associated with the first and second independently-controlled LNAs is configured to connect a capacitance between the gate and source terminal of the associated input transistor while only one of the first and second independently-controlled LNAs is enabled, and disconnect the capacitance while both of the first and second independently-controlled LNAs are enabled.

4 . The amplifier of claim 2 , wherein each gate capacitance module includes a capacitor and a switch coupled in series between the first and second terminals of the gate capacitance module.

5 . The amplifier of claim 1 , further including at least one gate capacitance module, each having a first terminal coupled to a gate of an associated input transistor of one of the independently-controlled LNAs, and a second terminal configured to be coupled to a ground reference.

6 . The amplifier of claim 5 , wherein each gate capacitance module associated with the first and second independently-controlled LNAs is configured to connect a capacitance between the gate of the associated input transistor and the ground reference while only one of the first and second independently-controlled LNAs is enabled, and disconnect the capacitance while both of the first and second independently-controlled LNAs are enabled.

7 . The amplifier of claim 5 , wherein each gate capacitance module includes a capacitor and a switch coupled in series between the first and second terminals of the gate capacitance module.

8 . The amplifier of claim 1 , further including at least one degeneration switch, each coupled to the source terminal of an associated input transistor of one of the independently-controlled LNAs and configured to be coupled to a degeneration component.

9 . The amplifier of claim 8 , wherein at least one degeneration switch is open when the source switch to which that degeneration switch is coupled is closed, and closed when the source switch to which that degeneration switch is coupled is open.

10 . The amplifier of claim 8 , wherein the degeneration component includes an inductor.

11 . The amplifier of claim 1 , further including a first degeneration switch coupled to the source terminal of the input transistor of the first independently-controlled LNA and configured to be coupled to a first degeneration component, and a second degeneration switch coupled to the source terminal of the input transistor of the second independently-controlled LNA and configured to be coupled to a second degeneration component.

12 . The amplifier of claim 11 , wherein the first degeneration switch is open and the second degeneration switch is closed when the source switch is closed, and wherein the first and the second degeneration switches are closed when the source switch is open.

13 . The amplifier of claim 11 , wherein the first and the second degeneration components each include an inductor.

14 . An amplifier including:
(a) a plurality of independently-controlled low noise amplifiers (LNAs), each including at least an input transistor having a source terminal; (b) a source switch coupled between the source terminal of the input transistor of a first of the independently-controlled LNAs and the source terminal of the input transistor of a second of the independently-controlled LNAs, the source switch configured to connect the source terminals while only one of the first and second independently-controlled LNAs is enabled, and disconnect the source terminals while both of the first and second independently-controlled LNAs are enabled; (c) at least one gate capacitance module, each having a first terminal coupled to a gate of an associated input transistor of one of the independently-controlled LNAs, and a second terminal coupled to the source terminal of the associated input transistor; and (d) at least one degeneration switch, each coupled to the source terminal of an associated input transistor of one of the independently-controlled LNAs and configured to be coupled to a degeneration component.

15 . The amplifier of claim 14 , wherein each gate capacitance module associated with the first and second independently-controlled LNAs is configured to connect a capacitance between the gate and source terminal of the associated input transistor while only one of the first and second independently-controlled LNAs is enabled, and disconnect the capacitance while both of the first and second independently-controlled LNAs are enabled.

16 . The amplifier of claim 14 , wherein each gate capacitance module includes a capacitor and a switch coupled in series between the first and second terminals of the gate capacitance module.

17 . The amplifier of claim 14 , further including at least additional one gate capacitance module, each having a first terminal coupled to a gate of an associated input transistor of one of the independently-controlled LNAs, and a second terminal configured to be coupled to a ground reference.

18 . The amplifier of claim 17 , wherein each additional gate capacitance module associated with the first and second independently-controlled LNAs is configured to connect a capacitance between the gate of the associated input transistor and the ground reference while only one of the first and second independently-controlled LNAs is enabled, and disconnect the capacitance while both of the first and second independently-controlled LNAs are enabled.

19 . The amplifier of claim 14 , wherein at least one degeneration switch is open when the source switch to which that degeneration switch is coupled is closed, and closed when the source switch to which that degeneration switch is coupled is open.

20 . The amplifier of claim 14 , wherein the degeneration component includes an inductor.

Assignees

• Psemi Corp

Inventors

• Ayranci Emre
• Sanner Miles

Classifications

• H03F2200/411

  the output amplifying stage of an amplifier comprising two power stages · CPC title

• H03F2200/387

  A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F1/565

  using inductive elements · CPC title